公开(公告)号：US20240213999A1

公开(公告)日：2024-06-27

申请号：US18519104

申请日：2023-11-27

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： YAN-HUI WU ,  Yao-Ming Lu ,  Tai-Cheng Lee ,  Chih-Lung Chen ,  Sheng-Yen Shih

IPC分类号： H03M1/46 ,  H03M1/06

CPC分类号： H03M1/462 ,  H03M1/0604 ,  H03M1/0626

摘要： A continuous-time delta-sigma modulator (CT-DSM) includes a loop filter, a pipelined successive-approximation register analog-to-digital converter (SAR ADC), a feedback circuit, an excess loop delay (ELD) compensation circuit, and a logic circuit. The loop filter generates a first intermediate signal according to an input signal, a feedback signal, and a compensation signal. The pipelined SAR ADC generates a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal. The feedback circuit generates the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal. The ELD compensation circuit generates the compensation signal according to at least one output signal of the feedback circuit. The logic circuit generates an output digital code according to the first digital code and the second digital code.