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公开(公告)号：US20240213999A1
公开(公告)日：2024-06-27
申请号：US18519104
申请日：2023-11-27
发明人： YAN-HUI WU , Yao-Ming Lu , Tai-Cheng Lee , Chih-Lung Chen , Sheng-Yen Shih
CPC分类号： H03M1/462 , H03M1/0604 , H03M1/0626
摘要： A continuous-time delta-sigma modulator (CT-DSM) includes a loop filter, a pipelined successive-approximation register analog-to-digital converter (SAR ADC), a feedback circuit, an excess loop delay (ELD) compensation circuit, and a logic circuit. The loop filter generates a first intermediate signal according to an input signal, a feedback signal, and a compensation signal. The pipelined SAR ADC generates a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal. The feedback circuit generates the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal. The ELD compensation circuit generates the compensation signal according to at least one output signal of the feedback circuit. The logic circuit generates an output digital code according to the first digital code and the second digital code.
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2.发明授权公开(公告)号：US12107597B2
公开(公告)日：2024-10-01
申请号：US17857621
申请日：2022-07-05
发明人： Shih-Hsiung Huang , Wei-Cian Hong , Sheng-Yen Shih
CPC分类号： H03M1/468 , H03M1/1245
摘要： A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.
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公开(公告)号：US11387839B2
公开(公告)日：2022-07-12
申请号：US17360083
申请日：2021-06-28
发明人： Sheng-Yen Shih , Shih-Hsiung Huang , Yu-Chang Chen
摘要： A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.
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公开(公告)号：US12113544B2
公开(公告)日：2024-10-08
申请号：US17864464
申请日：2022-07-14
发明人： Sheng-Yen Shih , Shih-Hsiung Huang , Wei-Cian Hong
CPC分类号： H03M1/38 , H03M1/1245 , H03M3/04
摘要： A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.
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公开(公告)号：US12068755B2
公开(公告)日：2024-08-20
申请号：US17944340
申请日：2022-09-14
发明人： Shih-Hsiung Huang , Wei-Cian Hong , Sheng-Yen Shih
摘要： A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.
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公开(公告)号：US11876526B2
公开(公告)日：2024-01-16
申请号：US17670536
申请日：2022-02-14
发明人： Shih-Hsiung Huang , Kai-Yue Lin , Wei-Jyun Wang , Sheng-Yen Shih
CPC分类号： H03M1/08
摘要： The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.
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