公开(公告)号：US20180061664A1

公开(公告)日：2018-03-01

申请号：US15689964

申请日：2017-08-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu SAITO ,  Takuya HAGIWARA

IPC: H01L21/3213 ,  H01L21/68 ,  H01L21/027 ,  H01L21/47 ,  H01L21/033 ,  H01L21/225

CPC classification number: H01L21/32139 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/2253 ,  H01L21/47 ,  H01L21/682

Abstract: A method of manufacturing a semiconductor device includes forming a reference pattern in an inspection pattern formation region, forming a first mask layer over a semiconductor substrate, while forming a first inspection pattern in the inspection pattern formation region, and measuring a first amount of misalignment of the first inspection pattern with respect to the reference pattern. The method further includes implanting ions into the semiconductor substrate using a first mask layer, removing the first mask layer and the first inspection pattern and then forming a second mask layer over the semiconductor substrate, while forming a second inspection pattern in the inspection pattern formation region, and measuring a second amount of misalignment of the second inspection pattern with respect to the reference pattern. In plan view, the second inspection pattern is larger than the first inspection pattern and covers the entire region where the first inspection pattern is formed.