公开(公告)号：US20240363424A1

公开(公告)日：2024-10-31

申请号：US18769858

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsin-Han Tsai ,  Wei-Chin Lee ,  Chia-Ching Lee ,  Hung-Chin Chung ,  Cheng-Lung Hung ,  Da-Yuan Lee

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/42372

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

公开(公告)号：US12131892B2

公开(公告)日：2024-10-29

申请号：US17643405

申请日：2021-12-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Feng-Ju Tsai ,  Shyue-Ru Doong

IPC: H01L21/67 ,  B08B5/02 ,  B08B5/04 ,  B08B9/032 ,  B08B9/035 ,  B08B15/00 ,  G03F7/00 ,  H01J37/32 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01J37/32862 ,  B08B5/02 ,  B08B5/04 ,  B08B9/0328 ,  B08B9/035 ,  B08B15/00 ,  G03F7/70933 ,  H01J37/3244 ,  H01J37/32724 ,  H01J37/32834 ,  H01L21/0206 ,  H01L21/0273 ,  H01L21/31138 ,  H01L21/67069 ,  H01J37/3211 ,  H01J2237/334

Abstract: A method includes the following steps. A wafer is disposed on a wafer-mounting surface of a wafer holder that is disposed in a chamber. The wafer-mounting surface is in parallel with a gravity direction. A gas is flown from a gas source to vacuum sealing device. An inductive coil wrapping around a vacuum sealing device excites the gas into plasma. The plasma is injected to the wafer.

公开(公告)号：US12122668B2

公开(公告)日：2024-10-22

申请号：US17858855

申请日：2022-07-06

Applicant: Brookhaven Science Associates, LLC

Inventor： Charles T. Black ,  Atikur Rahman ,  Matthew Eisaman ,  Ahsan Ashraf

IPC: B81C1/00 ,  B82Y30/00 ,  B82Y40/00 ,  G02B1/118 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/308 ,  H01L31/0236

CPC classification number: B81C1/00031 ,  B81C1/00111 ,  B82Y30/00 ,  G02B1/118 ,  G03F7/0002 ,  G03F7/405 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3086 ,  H01L31/02363 ,  B81C2201/0132 ,  B81C2201/0149 ,  B82Y40/00 ,  H01J2237/334 ,  Y02E10/50

Abstract: Methods for etching nanostructures in a substrate include depositing a patterned block copolymer on the substrate, the patterned block copolymer including first and second polymer block domains, applying a precursor to the patterned block copolymer to generate an infiltrated block copolymer, the precursor infiltrating into the first polymer block domain and generating a material in the first polymer block domain, applying a removal agent to the infiltrated block copolymer to generate a patterned material, the removal agent removing the first and second polymer block domains from the substrate, and etching the substrate, the patterned material on the substrate masking the substrate to pattern the etching. The etching may be performed under conditions to produce nanostructures in the substrate.

公开(公告)号：US12107044B2

公开(公告)日：2024-10-01

申请号：US16389672

申请日：2019-04-19

Applicant: Intel Corporation

Inventor： Marie Krysak ,  Kevin L. Lin ,  Robert Bristol ,  Charles H. Wallace

IPC: H01L23/528 ,  H01L21/027 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/0273 ,  H01L21/76816 ,  H01L21/76877

Abstract: Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.

公开(公告)号：US20240304444A1

公开(公告)日：2024-09-12

申请号：US18668432

申请日：2024-05-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01L21/0272 ,  H01L21/31144

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

公开(公告)号：US12087637B2

公开(公告)日：2024-09-10

申请号：US17120499

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsin-Han Tsai ,  Wei-Chin Lee ,  Chia-Ching Lee ,  Hung-Chin Chung ,  Cheng-Lung Hung ,  Da-Yuan Lee

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/42372

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

公开(公告)号：US12087578B2

公开(公告)日：2024-09-10

申请号：US17651851

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.

公开(公告)号：US12085858B2

公开(公告)日：2024-09-10

申请号：US16825388

申请日：2020-03-20

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Srinivas D. Nemani ,  Steven Hiloong Welch ,  Mangesh Ashok Bangar ,  Ellie Y. Yieh

IPC: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  H01L21/027 ,  H01L21/266 ,  H01L21/311

CPC classification number: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/31133

Abstract: A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.

公开(公告)号：US12014933B2

公开(公告)日：2024-06-18

申请号：US17562093

申请日：2021-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Yan-Hong Liu ,  Yeh-Chien Lin ,  Jin-Huai Chang

IPC: H01L21/3213 ,  H01L21/027 ,  H01L49/02

CPC classification number: H01L21/32135 ,  H01L21/0273 ,  H01L21/32139 ,  H01L28/20 ,  H01L28/60

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.

公开(公告)号：US20240112914A1

公开(公告)日：2024-04-04

申请号：US18121609

申请日：2023-03-15

Applicant: University of Electronic Science and Technology of China

Inventor： Bo ZHANG ,  Teng LIU ,  Wentong ZHANG ,  Nailong HE ,  Sen ZHANG ,  Ming QIAO ,  Zhaoji LI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32137 ,  H01L21/32139

Abstract: A new variable selective etching technology for thick SOI devices. An SOI material is etched by the following steps: (1) providing an SOI wafer; (2) depositing a composite hard mask with a variable selection ratio to replace a traditional hard mask with an invariable selection ratio; (3) applying a photoresist; (4) mask making, namely defining a to-be-etched region by using a photoetching plate; (5) etching the photoresist in the defined region; (6) etching the composite hard mask; (7) removing the photoresist; (8) etching top silicon by using a second etching method at a first selection ratio; and (9) etching a buried oxide layer by using a third etching method at a second selection ratio. The new variable selective etching technology avoids the damage to a side wall of a deep trench when the buried oxide layer is etched, and does not need to use an excessive thick hard mask.