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公开(公告)号:US20220416079A1
公开(公告)日:2022-12-29
申请号:US17901416
申请日:2022-09-01
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Machiko SATO , Akihiro SHIMOMURA
Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.
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公开(公告)号:US20240047572A1
公开(公告)日:2024-02-08
申请号:US18484710
申请日:2023-10-11
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Machiko SATO , Akihiro SHIMOMURA
CPC classification number: H01L29/7813 , H01L29/66734 , H01L29/1095
Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.
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公开(公告)号:US20210104625A1
公开(公告)日:2021-04-08
申请号:US17000533
申请日:2020-08-24
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Machiko SATO , Akihiro SHIMOMURA
Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.
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