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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250015175A1

    公开(公告)日：2025-01-09

    申请号：US18890208

    申请日：2024-09-19

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshinori KAYA ,  Katsumi EIKYU ,  Akihiro SHIMOMURA ,  Hiroshi YANAGIGAWA ,  Kazuhisa MORI

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

    Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230352521A1

    公开(公告)日：2023-11-02

    申请号：US18152574

    申请日：2023-01-10

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuta NABUCHI ,  Akihiro SHIMOMURA

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/0634 ,  H01L29/7813 ,  H01L29/0696 ,  H01L29/66734

    Abstract: An improved power MOSFET having a super junction structure is disclosed. The improved power MOSFET includes a plurality of unit cells UC, and each of the plurality of unit cells UC includes a column region PC1, a column region PC2, a pair of trenches TR formed between the column regions PC1 and PC2 in the X-direction and a pair of gate electrodes GE formed in the pair of trenches TR via gate insulating films (GI). The pair of trenches TR and the pair of gate-electrodes GE extend in Y-direction in a plan view. A plurality of column regions PC1 are formed so as to be spaced apart from one another along the Y-direction, and a width(L1) of the column region PC1 in the Y direction is wider than a width(L2) of the column region PC1 in the X direction.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230111142A1

    公开(公告)日：2023-04-13

    申请号：US17886049

    申请日：2022-08-11

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Katsumi EIKYU ,  Yuta NABUCHI ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

    Abstract: A semiconductor device includes a plurality of unit cells. Each of the plurality of unit cells has a pair of column regions, a pair of trenches formed between the pair of column regions in the X direction, and a pair of gate electrodes formed in the pair of trenches via a gate insulating film, respectively. The two unit cells adjacent in the X direction share one column region of the pair of column regions and are arranged to be symmetrical about the shared column region. Here, a distance between the two trenches, which are adjacent with the one column region interposed therebetween, of the trenches in the two adjacent unit cells is different from a distance between the pair of trenches in the one unit cell.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150325696A1

    公开(公告)日：2015-11-12

    申请号：US14804819

    申请日：2015-07-21

    Applicant: Renesas Electronics Corporation

    Inventor： Akihiro SHIMOMURA ,  Yutaka AKIYAMA ,  Saya SHIMOMURA ,  Yasutaka NAKASHIBA

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

    CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

    Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

    Abstract translation: 一种半导体器件，包括第一导体层，形成在第一导体层上的第二导体层，形成在第二导体层上的第三导体层，通过第三导体层并形成在第二导体层中的栅极沟槽， 形成在栅极沟槽的内壁上的第一绝缘膜，形成在栅极沟槽的内壁上的第二绝缘膜，形成在栅极沟槽中的第一掩埋导体层，形成在栅极沟槽中的栅电极，第四绝缘膜 在第一掩埋导体层的下端形成的第二导电类型的导体层和栅极沟槽的下端，以及形成在第三导体层上的第一导电类型的第五导电层。 第一绝缘膜比第二绝缘膜厚。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140284709A1

    公开(公告)日：2014-09-25

    申请号：US14204145

    申请日：2014-03-11

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Akihiro SHIMOMURA ,  Yutaka AKIYAMA ,  Saya SHIMOMURA ,  Yasutaka NAKASHIBA

    IPC: H01L29/78 ,  H01L29/423

    CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

    Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

    Abstract translation: 在漂移层中形成第二导电类型的掩埋层和第二导电类型的下层。 边界绝缘膜形成在第二导电类型的掩埋层的横向部分与漂移层之间的边界中。 第二导电类型的下层与第二导电类型的掩埋层的下端和边界绝缘膜的下端接触。 第二导电类型的掩埋层与源电极电连接。 在第二导电类型的掩埋层的表面层中形成第二导电类型的高浓度层。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20240395878A1

    公开(公告)日：2024-11-28

    申请号：US18630051

    申请日：2024-04-09

    Applicant: Renesas Electronics Corporation

    Inventor： Yuta NABUCHI ,  Akihiro SHIMOMURA

    IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: A trench TR1 and a trench TR2 are formed in a semiconductor substrate SUB so as to reach a predetermined depth from the upper surface (TS) of the semiconductor substrate SUB. A field plate electrode FP is formed at a lower portion of the trench TR1, and a gate electrode GE1 is formed at an upper portion of the trench TR1. A gate electrode GE2 is formed inside the trench TR2. The depth of the trench TR1 is deeper than the depth of the trench TR2. The trench TR1 extends in the Y direction, and the trench TR2 extends in the X direction. The trench TR1 and the trench TR2 are in communication with each other. The gate electrode GE1 and the gate electrode GE2 are integrated with each other.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20230411512A1

    公开(公告)日：2023-12-21

    申请号：US18189541

    申请日：2023-03-24

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Akihiro SHIMOMURA ,  Masami SAWADA

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7813 ,  H01L29/66734

    Abstract: An improved structure and a manufacturing method of a vertical type power MOSFET having a super junction configuration is disclosed. The improved structure and the manufacturing method of the vertical type power MOSFET comprising: a step of preparing a semiconductor substrate SB including an n-type semiconductor layer SL and a p-type epitaxial layer EP on the semiconductor layer SL; a step of forming a trench GT in the p-type epitaxial layer EP by using an etching mask with a predetermined opening width; and a step of introducing an n-type impurity into a bottom portion of the trench GT using the etching mask with the predetermined opening width, whereby forming an n-type column NC at the bottom of trench GT and reaching the semiconductor layer SL.

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