公开(公告)号：US20210111256A1

公开(公告)日：2021-04-15

申请号：US16601234

申请日：2019-10-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naoki TAKIZAWA ,  Tatsuyoshi MIHARA

IPC: H01L21/28 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/66

Abstract: After the step of polishing, a part of each of each gate electrode is removed such that the upper surface of each gate electrode is located closer than the damaged region formed in the gate insulating film located between the gate electrodes to the main surface of the semiconductor substrate in cross-section view. Thus, it is possible to suppress the occurrence of a short-circuit defect during the operation of the semiconductor device.

公开(公告)号：US20190304544A1

公开(公告)日：2019-10-03

申请号：US16352273

申请日：2019-03-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoya SAITO ,  Naoki TAKIZAWA

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/04

Abstract: It is to optimize the initial threshold voltages of each memory area in a semiconductor memory device including a plurality of memory areas. A semiconductor memory device according to the embodiment includes a first memory area for storing data and a second memory area for storing the information related to the first memory area. In the respective memory cells arranged in the first and the second memory areas, the initial threshold voltages of the memory cells arranged in the second memory area are designed to be higher than those of the memory cells arranged in the first memory area.

公开(公告)号：US20240274697A1

公开(公告)日：2024-08-15

申请号：US18433803

申请日：2024-02-06

Applicant: Renesas Electronics Corporation

Inventor： Naoki TAKIZAWA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

Abstract: Two resistance elements are each formed so as to overlap a portion of each of a gate pad and a gate wiring in a plan view, and are electrically connected to the gate pad and the gate wiring. A p-type well region is formed so as to overlap a portion of each of the two insulating films, the two resistance elements, the gate pad, the gate wiring, and the emitter electrode in the plan view. The emitter electrode includes a convex portion that protrudes toward a gate pad side in a Y direction in the plan view. The convex portion is located between the two resistance elements in the plan view. The convex portion and the well region are electrically connected via a hole formed in an interlayer insulating film.