公开(公告)号：US20180013414A1

公开(公告)日：2018-01-11

申请号：US15496400

申请日：2017-04-25

Applicant: Renesas Electronics Corporation

Inventor： Sakae NAKAJIMA

IPC: H03K17/082 ,  H01L27/092 ,  H01L27/02 ,  H03K17/22 ,  H02H5/04

Abstract: There has been a problem in semiconductor apparatuses of related art in which a circuit operation cannot be returned after a reverse current occurred. In one embodiment, a semiconductor apparatus includes a timer block configured to count up a count value to a predetermined value in response to a control signal being enabled, the control signal instructing a power MOS transistor to be turned on, and a protection transistor including a drain connected to a gate of the power MOS transistor, a source and a back gate connected to a source of the power MOS transistor, and an epitaxial layer in which the power MOS transistor is formed, the epitaxial layer being supplied with a power supply voltage. The protection transistor short-circuits the source and gate of the power MOS transistor in response to an output voltage of the power MOS transistor meeting a predetermined condition and the count value reaching the predetermined value. The timer block resets the count value when the output voltage of the power MOS transistor no longer meets the predetermined condition.

公开(公告)号：US20150022247A1

公开(公告)日：2015-01-22

申请号：US14508432

申请日：2014-10-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akihiro NAKAHARA ,  Sakae NAKAJIMA

IPC: H03K17/16 ,  H03K17/04

CPC classification number: H03K17/161 ,  H01L27/0716 ,  H01L27/088 ,  H01L29/7813 ,  H01L29/7835 ,  H03K17/04 ,  H03K17/081 ,  H03K17/0822

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract translation: 功率半导体器件包括输出晶体管，与输出晶体管的栅极连接的控制电路，从第一节点到接地端子的第一放电路径，以及从第一节点到接地端子的第二放电路径。 在通常的关闭中，仅使用第一放电路线。 当发生负载异常时，使用第一和第二放电路径。 第二放电路径包含放电晶体管和逆流防止装置。 放电晶体管连接在第一节点和第二节点之间。 逆流防止装置防止从第三节点到第二节点的电流流动。 至少在OFF期间，控制电路将放电晶体管的栅极电压设定为高电平。