公开(公告)号：US20190198402A1

公开(公告)日：2019-06-27

申请号：US16291620

申请日：2019-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki AONO ,  Tetsuya YOSHIDA ,  Makoto OGASAWARA ,  Shinichi OKAMOTO

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/76237 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region. surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation legion and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

公开(公告)号：US20160141289A1

公开(公告)日：2016-05-19

申请号：US14934745

申请日：2015-11-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki AONO ,  Tetsuya YOSHIDA ,  Makoto OGASAWARA ,  Shinichi OKAMOTO

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/76237 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract translation: 提供具有提高的可靠性的半导体器件。 主要由氧化硅组成的元件隔离区被埋在形成于半导体衬底中的沟槽中。 由元件隔离区包围的有源区中的半导体衬底在其上具有用于MISFET的栅极经由栅极绝缘膜。 栅电极部分地延伸在元件隔离区上方，并且沟槽具有氮化的内表面。 在栅电极下方，氟被引入到元件隔离区域和MISFET的沟道区域之间的边界附近。

公开(公告)号：US20180122930A1

公开(公告)日：2018-05-03

申请号：US15690233

申请日：2017-08-29

Applicant: Renesas Electronics Corporation

Inventor： Shinichi OKAMOTO ,  Tsutomu OKAZAKI

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234

Abstract: There is improved performance of a semiconductor device including a fin-type low-withstand-voltage transistor and a fin-type high-withstand-voltage transistor. A low-withstand-voltage transistor is formed on each of a plurality of first fins isolated from each other by a first element isolation film, and a high-withstand-voltage transistor, which has a channel region including tops and side surfaces of a plurality of second fins and a top of a semiconductor substrate between the second fins adjacent to each other, is formed. At this time, a top of a second element isolation film surrounding the second fins including part of the channel region of one high-withstand-voltage transistor is lower than a top of the first element isolation film.