公开(公告)号：US20170092555A1

公开(公告)日：2017-03-30

申请号：US15280308

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Hideki AONO ,  Makoto OGASAWARA ,  Naohito SUZUMURA ,  Tetsuya YOSHIDA

IPC: H01L21/66

CPC classification number: H01L22/34 ,  G01R31/2621 ,  G01R31/2628 ,  G01R31/2642 ,  H01L22/14 ,  H01L22/26 ,  H01L29/785

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

公开(公告)号：US20230197827A1

公开(公告)日：2023-06-22

申请号：US18052382

申请日：2022-11-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Zhichao LIN ,  Koji OGATA ,  Yukio TAKAHASHI ,  Tomohiro IMAI ,  Tetsuya YOSHIDA

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L29/66348 ,  H01L29/7397 ,  H01L29/0638 ,  H01L29/0834 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/26513

Abstract: A gate electrode is formed inside a trench via a gate insulating film. The gate insulating film formed on a semiconductor substrate is removed. An insulating film is formed on the semiconductor substrate. A p-type base region is formed in the semiconductor substrate. An n-type emitter region is formed in the base region. Hydrogen annealing process is performed to the semiconductor substrate. A boundary between the base region and the emitter region is located at a position deeper than the insulating film formed between a side surface of the trench and the gate insulating film.

公开(公告)号：US20190097018A1

公开(公告)日：2019-03-28

申请号：US16055050

申请日：2018-08-04

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya YOSHIDA

IPC: H01L29/51 ,  H01L29/417 ,  H01L27/12 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66

Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has, on a SOI substrate thereof having a semiconductor substrate, an insulating layer, and a semiconductor layer, a gate insulating film having an insulating film and a high dielectric constant film. The high dielectric constant film has a higher dielectric constant than a silicon oxide film and includes a first metal and a second metal. In the high dielectric constant film, the ratio of the number of atoms of the first metal to the total number of atoms of the first metal and the second metal is equal to or more than 75%, and less than 100%.

公开(公告)号：US20170287795A1

公开(公告)日：2017-10-05

申请号：US15630725

申请日：2017-06-22

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Tetsuya YOSHIDA ,  Koetsu SAWAI

IPC: H01L21/66 ,  H01L21/265 ,  H01L21/768 ,  G01R31/307 ,  H01L23/535 ,  H01L23/544 ,  H01L27/11 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

公开(公告)号：US20230411502A1

公开(公告)日：2023-12-21

申请号：US18185065

申请日：2023-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji OGATA ,  Tetsuya YOSHIDA ,  Yukio TAKAHASHI

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/66348 ,  H01L29/0696

Abstract: A semiconductor device includes an n-type semiconductor substrate, a trench, a gate electrode formed in the trench via the gate insulating film, a p-type base region formed in the semiconductor substrate, and an n-type emitter region formed in the base region. The trench extends in a Y direction, in a plan view. Adjacent ones of a plurality of emitter regions are formed to be spaced apart from each other by a distance, along the Y direction. The distance is wider than ⅕ of a width of each of the emitter regions in the Y direction and narrower than the width.

公开(公告)号：US20220115270A1

公开(公告)日：2022-04-14

申请号：US17480746

申请日：2021-09-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya YOSHIDA ,  Tomohiro TOMIZAWA

IPC: H01L21/768 ,  H01L29/66 ,  H01L27/12 ,  H01L21/66

Abstract: A first MISFET is formed on a semiconductor layer of an SOI substrate in a circuit region and a second MISFET composing a TEG for VC inspection is formed on the semiconductor layer of the SOI substrate in a TEG region. An interlayer insulating film is formed, contact holes are formed in the interlayer insulating film, and plugs are formed in the contact holes, respectively. In the TEG region, the plugs include a plug electrically connected to both the semiconductor substrate composing the SOI substrate and the semiconductor layer composing the SOI substrate.

公开(公告)号：US20170309728A1

公开(公告)日：2017-10-26

申请号：US15468862

申请日：2017-03-24

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya YOSHIDA ,  Tetsuo ITO ,  Koji OGATA ,  Hideki AONO

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/266 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66568 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/78603

Abstract: In a process of implanting ions of an n-type impurity for threshold control into a semiconductor substrate surrounded by an element isolation portion, a resist pattern is formed such that the resist pattern covers a divot formed at a boundary portion of the element isolation portion with an SOI layer. Thus, since ions of the n-type impurity are not implanted into the divot, an etching rate of the divot in a cleaning process or the like is not accelerated, and etching can be suppressed. As a result, a BOX layer is prevented from becoming thin, so that degradation of a TDDB characteristic of the BOX layer can be prevented.

公开(公告)号：US20160197021A1

公开(公告)日：2016-07-07

申请号：US15067173

申请日：2016-03-10

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Tetsuya YOSHIDA ,  Koetsu SAWAI

IPC: H01L21/66 ,  H01L23/532 ,  H01L27/11 ,  H01L23/535

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

公开(公告)号：US20150179673A1

公开(公告)日：2015-06-25

申请号：US14470846

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Tetsuya YOSHIDA ,  Koetsu SAWAI

IPC: H01L27/12 ,  H01L23/544 ,  H01L21/66 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

Abstract translation: 当执行用于TEG的VC检查时，通过增加接触插塞的发射强度容易地检测是否发生接触插塞的任何故障，从而提高了半导体器件的可靠性。 SRAM的元件结构形成在芯片区域的SOI衬底上。 此外，在TEG区域中，在从SOI层和BOX膜露出的半导体衬底上形成接触插塞连接到半导体衬底的SRAM的元件结构，作为用于VC检查的TEG。

公开(公告)号：US20240290791A1

公开(公告)日：2024-08-29

申请号：US18433827

申请日：2024-02-06

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya YOSHIDA ,  Shibun TSUDA ,  Hideki MAKIYAMA

IPC: H01L27/12 ,  H01L21/265 ,  H01L21/84 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/26513 ,  H01L21/84 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/7838

Abstract: A low withstand voltage MISFET and a high withstand voltage MISFET are formed on an SOI substrate. An ON operation and an OFF operation of the low withstand voltage MISFET are controlled by a first gate potential to be supplied to a first gate electrode and a back gate potential to be supplied to a first well region. An ON operation and an OFF operation of the high withstand voltage MISFET are controlled by a second gate potential to be supplied to a second gate electrode in a state where a second well region is electrically floating. An absolute value of a second power supply potential to be supplied to a second impurity region is larger than an absolute value of a first power supply potential to be supplied to a first impurity region.