公开(公告)号：US20150280571A1

公开(公告)日：2015-10-01

申请号：US14742045

申请日：2015-06-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji TATENO ,  Takahiro NOMIYAMA ,  Yoshinao MIURA ,  Hideo ISHII

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M1/38 ,  H02M3/1588 ,  Y02B70/1466

Abstract: Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

Abstract translation: 公开了一种功率转换电路，其抑制基于常通晶体管的开关元件的通流电流。 功率转换电路包括彼此串联耦合以形成半桥电路的高侧晶体管和低侧晶体管，以及互补驱动高边晶体管的栅极的两个驱动电路，以及 的低端晶体管。 高边晶体管是常关晶体管。 低端晶体管是常开晶体管。

公开(公告)号：US20140176093A1

公开(公告)日：2014-06-26

申请号：US14064522

申请日：2013-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro NOMIYAMA ,  Koji TATENO ,  Daisuke KONDO

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H02M2001/0058 ,  H03K17/122 ,  H03K17/164 ,  H03K2217/0036 ,  H03K2217/0063 ,  H03K2217/0072 ,  Y02B70/1491

Abstract: A switching loss is reduced by reducing a deviation from the operational principle of zero-volt switching (ZVS). A semiconductor integrated circuit includes high-side switch elements Q11 and Q12, a low-side switch element Q2, and a controller CNT. A decoupling capacitance Cin is coupled between one end of a high-side element and an earth potential, and the high-side element includes the first and second transistors Q11 and Q12 coupled in parallel. In changing the high-side elements from an on-state to an off-state, CNT controls Q12 from an on-state to an off-state by delaying Q12 relative to Q11. Q11 and Q12 are divided into a plurality of parts inside a semiconductor chip Chip 1, a plurality of partial first transistors formed by dividing Q11 and a plurality of partial second transistors formed by dividing Q12 are alternately arranged in an arrangement direction of Q11 and Q12, inside the semiconductor chip Chip 1.

Abstract translation: 通过减少与零电压开关（ZVS）的工作原理的偏差来减少开关损耗。 半导体集成电路包括高侧开关元件Q11和Q12，低侧开关元件Q2和控制器CNT。 去耦电容Cin耦合在高侧元件的一端和地电位之间，高侧元件包括并联耦合的第一和第二晶体管Q11和Q12。 在将高端元件从导通状态切换到截止状态时，CNT通过相对于Q11延迟Q12，将Q12从导通状态切换到关闭状态。 Q11和Q12被分成半导体芯片芯片1内的多个部分，通过划分Q11而形成的多个局部第一晶体管和由Q12分割成的多个部分第二晶体管沿Q11和Q12的排列方向交替布置， 在半导体芯片芯片1内。