公开(公告)号：US20120198452A1

公开(公告)日：2012-08-02

申请号：US13445051

申请日：2012-04-12

申请人： RICHARD L. ARNDT ,  NARESH NAYAR ,  CHRISTOPHER FRANCOIS ,  KARTHICK RAJAMANI ,  FREEMAN L. RAWSON, III ,  RANDAL C. SWANBERG

发明人： RICHARD L. ARNDT ,  NARESH NAYAR ,  CHRISTOPHER FRANCOIS ,  KARTHICK RAJAMANI ,  FREEMAN L. RAWSON, III ,  RANDAL C. SWANBERG

IPC分类号： G06F9/455

CPC分类号： G06F9/45533 ,  G06F9/45541 ,  G06F2009/45575

摘要： A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.

摘要翻译： 在逻辑分区的数据处理系统中提供一种机制，用于控制虚拟处理器的空闲状态的退出的深度和等待时间。 一个虚拟化层产生一个雪松延迟设置信息（CLSI）数据。 响应于引导逻辑分区，虚拟化层将CLSI数据传送到逻辑分区的操作系统（OS）。 OS根据CLSI数据确定在OS控制下的虚拟处理器的特定空闲状态。 响应于调用虚拟化层的OS，OS将虚拟处理器的特定空闲状态传送到虚拟化层，以将特定的空闲状态和唤醒特性分配给虚拟处理器。

公开(公告)号：US20170139857A1

公开(公告)日：2017-05-18

申请号：US15334951

申请日：2016-10-26

申请人： RICHARD L. ARNDT ,  FLORIAN A. AUERNHAMMER

发明人： RICHARD L. ARNDT ,  FLORIAN A. AUERNHAMMER

IPC分类号： G06F13/26 ,  G06F12/122

CPC分类号： G06F13/26 ,  G06F9/4881 ,  G06F9/542 ,  G06F12/12 ,  G06F12/122 ,  G06F13/24 ,  G06F13/28 ,  G06F13/4068 ,  G06F2212/70

摘要： A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies an event target number, a number of bits to ignore, an event source number, and an event priority. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.