公开(公告)号：US20240332430A1

公开(公告)日：2024-10-03

申请号：US18618797

申请日：2024-03-27

Applicant: ROHM CO., LTD.

Inventor： Yuji KOGA

IPC: H01L29/808 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/808 ,  H01L29/0847 ,  H01L29/1058 ,  H01L29/1066

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a bottom gate region of a first conductivity type and formed in a semiconductor layer; a top gate region of the first conductivity type and formed in a surface layer portion of a first surface of the semiconductor layer, wherein the top gate region faces the bottom gate region along a thickness direction of the semiconductor layer; a source region of a second conductivity type, formed in the surface layer portion of the first surface of the semiconductor layer and separated from the top gate region in a direction along the first surface; and a drain region of the second conductivity type, formed in the surface layer portion of the first surface of the semiconductor layer and separated from the top gate region at an opposite side of the source region in the direction along the first surface.

公开(公告)号：US20200312806A1

公开(公告)日：2020-10-01

申请号：US16832946

申请日：2020-03-27

Applicant: ROHM CO., LTD.

Inventor： Shoji TAKEI ,  Yuji KOGA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.

公开(公告)号：US20250048722A1

公开(公告)日：2025-02-06

申请号：US18789406

申请日：2024-07-30

Applicant: ROHM CO., LTD.

Inventor： Shoji TAKEI ,  Yuji KOGA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor device including a diode. The semiconductor device includes: a semiconductor substrate; an n-type diffusion region selectively formed in a surface layer portion of a p-type epitaxial layer; an n-type buried layer sandwiched between the semiconductor substrate and the n-type diffusion region and having an impurity concentration greater than that of the n-type diffusion region; a p-type anode contact region formed in a surface layer portion of a first main surface of the semiconductor substrate; an n-type first cathode contact region formed in a surface layer portion of the n-type diffusion region and in a surface layer portion of the first main surface; a p-type well region extending along a depth direction from the first main surface outside the first cathode contact region to reach the n-type buried layer, dividing the n-type diffusion region along a direction along the first main surface.

公开(公告)号：US20240405074A1

公开(公告)日：2024-12-05

申请号：US18797966

申请日：2024-08-08

Applicant: ROHM CO., LTD.

Inventor： Yuji KOGA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/808

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface at an opposite side thereto, a bottom gate region of a first conductivity type that is formed in the semiconductor layer, and a top gate region of the first conductivity type that is formed in a surface layer portion of the first surface of the semiconductor layer and faces the bottom gate region in a thickness direction of the semiconductor layer, the bottom gate region includes a first bottom gate region at the source region side and a second bottom gate region at the drain region side, and an interval in the thickness direction between the second bottom gate region and the top gate region is greater than an interval in the thickness direction between the first bottom gate region and the top gate region.

公开(公告)号：US20220344299A1

公开(公告)日：2022-10-27

申请号：US17860291

申请日：2022-07-08

Applicant: ROHM CO., LTD.

Inventor： Shoji TAKEI ,  Yuji KOGA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.

公开(公告)号：US20240170436A1

公开(公告)日：2024-05-23

申请号：US18423463

申请日：2024-01-26

Applicant: ROHM CO., LTD.

Inventor： Shoji TAKEI ,  Yuji KOGA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L24/29 ,  H01L23/3114 ,  H01L23/53228 ,  H01L2224/29155 ,  H01L2924/18161

Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.

公开(公告)号：US20220254692A1

公开(公告)日：2022-08-11

申请号：US17665019

申请日：2022-02-04

Applicant: ROHM Co., LTD.

Inventor： Yuji KOGA

IPC: H01L21/66

Abstract: Provided is a semiconductor element including a semiconductor substrate; a semiconductor layer laminated to the semiconductor substrate, and having a circuit formed within the semiconductor layer; a conductive layer disposed on an opposite side of the semiconductor layer from the semiconductor substrate and including a part electrically connected to the circuit; and a conductive portion disposed between the semiconductor layer and the conductive layer, and electrically connected to the conductive layer. The conductive layer includes a check pattern not electrically connected to the circuit, and the conductive portion includes a superimposition portion superimposed on the check pattern as viewed in a thickness direction of the semiconductor substrate.