公开(公告)号：US20220014202A1

公开(公告)日：2022-01-13

申请号：US17485119

申请日：2021-09-24

申请人： Rahul Pal ,  Dheeraj Subbareddy ,  Mahesh Kumashikar ,  Dheemanth Nagaraj ,  Rajesh Vivekanandham ,  Anshuman Thakur ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Atul Maheshwari

发明人： Rahul Pal ,  Dheeraj Subbareddy ,  Mahesh Kumashikar ,  Dheemanth Nagaraj ,  Rajesh Vivekanandham ,  Anshuman Thakur ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Atul Maheshwari

IPC分类号： H03K19/17796 ,  G06F15/78 ,  G06F30/34 ,  H03K19/17758

摘要： The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

公开(公告)号：US20190041895A1

公开(公告)日：2019-02-07

申请号：US15952169

申请日：2018-04-12

申请人： Yingyu Miao ,  Gerald Pasdast ,  Peipei Wang ,  Mahesh Kumashikar

发明人： Yingyu Miao ,  Gerald Pasdast ,  Peipei Wang ,  Mahesh Kumashikar

IPC分类号： G06F1/10 ,  H03K5/15 ,  H01L23/66 ,  H01L25/065

摘要： A processing device includes a package, a plurality of dies disposed on the package, where each die comprises a clock receiver, and a single common clock source to generate a common clock signal. The processing device also includes a clock distribution circuitry coupled to the single common clock source. The clock distribution circuitry distributes the common clock signal from the single common clock source to each of the plurality of dies individually. The clock distribution circuitry includes a first group of terminated transmission lines. The first group of terminated transmission lines includes a first terminated transmission line, a second terminated transmission line, and a first termination resistor coupled between the first terminated transmission line and the second terminated transmission line. The first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source.