公开(公告)号：US20220013488A1

公开(公告)日：2022-01-13

申请号：US17484922

申请日：2021-09-24

申请人： Mahesh K. Kumashikar ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Atul Maheshwari

发明人： Mahesh K. Kumashikar ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Atul Maheshwari

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L25/00

摘要： An integrated circuit device includes multiple microbumps and a top programmable fabric die including a first programmable fabric and a first microbump interface coupled to the multiple microbumps. The integrated circuit device also includes a base programmable fabric die having a second programmable fabric and a second microbump interface coupled to the first microbump interface via a coupling to the multiple microbumps. The top programmable fabric die and the base programmable fabric die have a same design. Moreover, the top programmable fabric die and the base programmable fabric die are arranged in a three-dimensional die arrangement with the top programmable fabric die flipped above the base programmable fabric die.

公开(公告)号：US09293426B2

公开(公告)日：2016-03-22

申请号：US13631669

申请日：2012-09-28

申请人： MD Altaf Hossain ,  Scott A. Gilbert

发明人： MD Altaf Hossain ,  Scott A. Gilbert

IPC分类号： H01L23/64 ,  H01L23/13 ,  H01L25/16 ,  H05K1/11 ,  H01L23/498 ,  H05K1/18

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/7687 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5222 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/16 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/16 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H04M1/0266 ,  H05K1/111 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/09472 ,  H05K2201/10015 ,  H05K2201/10378 ,  Y02P70/611 ,  H01L2924/00

摘要： A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

摘要翻译： 公开了一种包括安装在封装衬底的空腔内的电容器的封装结构。 封装结构可以另外包括安装到封装衬底的管芯侧表面的管芯，并且封装衬底的相对的焊盘侧表面可以安装到印刷电路板（PCB）。 电容器可以安装在形成在封装衬底的裸片侧表面或封装衬底的焊盘侧表面中的空腔内。 在腔内安装电容可能会降低封装的外形尺寸。 模具可以安装在形成在封装衬底的裸片侧表面中的空腔内。 将封装连接到PCB的焊球可以安装在形成在封装基板和PCB中的一个或两者中的一个或多个空腔内。

公开(公告)号：US20140317343A1

公开(公告)日：2014-10-23

申请号：US14182053

申请日：2014-02-17

申请人： Md Altaf Hossain ,  Kevin J. Doran ,  Nagi Aboulenein

发明人： Md Altaf Hossain ,  Kevin J. Doran ,  Nagi Aboulenein

IPC分类号： G06F13/16 ,  G11C7/10 ,  G11C7/22

CPC分类号： G06F13/1689 ,  G06F13/1684 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229 ,  Y02D10/14

摘要： Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.

公开(公告)号：US20140116765A1

公开(公告)日：2014-05-01

申请号：US13664264

申请日：2012-10-30

申请人： MD Altaf Hossain ,  Jin Zhao ,  John T. Vu

发明人： MD Altaf Hossain ,  Jin Zhao ,  John T. Vu

IPC分类号： H05K1/16 ,  H05K3/30

CPC分类号： H05K1/183 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0326 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/32 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/09709 ,  H05K2201/0989 ,  H05K2201/10734 ,  Y10T29/4913

摘要： Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及具有诸如电感器，电容器，电阻器和相关技术和配置的集成无源器件的电路板。 在一个实施例中，一种装置包括具有与第一表面相对的第一表面和第二表面的电路板，以及与电路板成一体的无源器件，该无源器件具有被配置为与管芯的电力耦合的输入端子， 与输入端子电耦合的输出端子以及设置在电路板的第一表面和第二表面之间的电气路由特征，并且与输入端子和输出端子耦合以在输入端子和输出端子之间布置电力 ，其中所述输入端子包括被配置为接收包括所述管芯的封装组件的焊球连接的表面。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140092572A1

公开(公告)日：2014-04-03

申请号：US13631683

申请日：2012-09-28

申请人： MD Altaf Hossain ,  Scott A. Gilbert

发明人： MD Altaf Hossain ,  Scott A. Gilbert

IPC分类号： H05K1/11 ,  H05K13/00

CPC分类号： H05K3/3436 ,  B23K31/02 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/3478 ,  H05K2201/09745 ,  H05K2203/041 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

摘要： A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

摘要翻译： 公开了一种在阵列的高应力区域具有较大焊球的BGA结构。 较大的焊球具有较高的焊点可靠性（SJR），因此可被指定为关键功能（CTF），因此高应力区域中较大的焊球在电路板和安装在其上的封装之间承载输入/输出信号。 通过将封装基板，电路板或封装基板和电路板两者中的每个球凹入来容纳较大的焊球。 另外，公开了一种用于安装具有不同平均直径的多个焊球的球附着方法。

公开(公告)号：US20240348253A1

公开(公告)日：2024-10-17

申请号：US18757170

申请日：2024-06-27

申请人： Atul Maheshwari ,  Mahesh K. Kumashikar ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru ,  Jeffrey Christopher Chromczak

发明人： Atul Maheshwari ,  Mahesh K. Kumashikar ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru ,  Jeffrey Christopher Chromczak

IPC分类号： H03K19/17728 ,  G06F30/343 ,  H03K19/17736 ,  H03K19/17758 ,  H03K19/17796

CPC分类号： H03K19/17728 ,  G06F30/343 ,  H03K19/17744 ,  H03K19/17796 ,  H03K19/17758

摘要： Systems or methods of the present disclosure may provide an integrated circuit device that implements one region definition, which may decrease design complexity, decrease software complexity, and increase ease of use. For example, the integrated circuit device may include programmable logic that implements one region definition. The region definition may include circuitry that may implement three-dimensional (3D) input/output circuitry, 2.5D input/output circuitry, circuitry for intra-die communication, circuitry for inter-package communication, or any combination thereof. By implementing one region definition on the integrated circuit device, time spent defining each programmable logic region may be reduced or eliminated, thereby reducing design complexity software complexity associated with the integrated circuit device.

公开(公告)号：US20240346224A1

公开(公告)日：2024-10-17

申请号：US18757046

申请日：2024-06-27

申请人： Mahesh K. Kumashikar ,  Atul Maheshwari ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru

发明人： Mahesh K. Kumashikar ,  Atul Maheshwari ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru

IPC分类号： G06F30/392 ,  G06F30/33 ,  G06F119/10

CPC分类号： G06F30/392 ,  G06F30/33 ,  G06F2119/10

摘要： Systems or methods of the present disclosure may provide a multi-chip package with two or more integrated circuit devices that each include hybrid bumps. The hybrid bumps may include bumps of different sizes to facilitate different types of communication. For example, the hybrid bumps may include a first bump with fine pitch for die-to-die communication and/or a second bump with a large pitch for off-package communication. The multi-chip package may include a bridge to facilitate signal transfer between the integrated circuit device with the hybrid bumps and other components within the multi-chip package. Additionally or alternatively, the multi-chip package may include an interconnect to facilitate signal transfer between two integrated circuit devices. The interconnect may include fine pitch bumps, which may be translated by an interposer to a pitch size of the bridge. As such, the interconnect may facilitate die-to-die communication and/or off-package communication.

公开(公告)号：US20230024515A1

公开(公告)日：2023-01-26

申请号：US17957210

申请日：2022-09-30

申请人： Atul Maheshwari ,  Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Mahesh A. Iyer

发明人： Atul Maheshwari ,  Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Mahesh A. Iyer

IPC分类号： H03K19/17736 ,  H01L23/528

摘要： A programmable logic device may include a first layer formed using backside metallization on a back plane of the programmable logic device and a second fabric routing circuitry to route second data within the programmable fabric. The first layer may include first fabric routing circuitry to route first data within a programmable fabric of the programmable logic device, and clock routing circuitry to route clock signals within the programmable fabric.

公开(公告)号：US20220113788A1

公开(公告)日：2022-04-14

申请号：US17559632

申请日：2021-12-22

申请人： Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Atul Maheshwari ,  Yuet Li ,  MD Altaf Hossain

发明人： Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Atul Maheshwari ,  Yuet Li ,  MD Altaf Hossain

IPC分类号： G06F1/3287 ,  G06F30/343 ,  G06F1/324

摘要： The present disclosure describes programmable logic that may be operated in a turbo processing mode to cause an ongoing operation to be completed faster than a scheduled completion time. With at least some of the remaining time to the scheduled completion time, power savings may be realized by operating the programmable logic into a deep sleep mode, where configuration memory associated with the programmable logic may be set to a suitable voltage level as to not cause data loss at lower or zero voltage levels but otherwise realize power savings relative to an amount of power consumed during average processing operations.

公开(公告)号：US20140133075A1

公开(公告)日：2014-05-15

申请号：US14162002

申请日：2014-01-23

申请人： Md Altaf Hossain ,  Cliff C. Lee ,  David W. Browning ,  Itai M. Pines ,  Brian P. Kelly

发明人： Md Altaf Hossain ,  Cliff C. Lee ,  David W. Browning ,  Itai M. Pines ,  Brian P. Kelly

IPC分类号： H05K1/11

CPC分类号： H05K1/111 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/12042 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09972 ,  H05K2201/10378 ,  H01L2924/014 ,  H01L2924/00

摘要： The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.

摘要翻译： 本公开涉及被制造为具有重叠的连接区域的微电子衬底，例如插入件，母板，测试平台等，使得不同的微电子器件，例如微处理器，芯片组，图形处理器件，无线器件，存储器 设备，专用集成电路等可以交替地附接到微电子基板以形成功能微电子封装。