公开(公告)号：US20220014202A1

公开(公告)日：2022-01-13

申请号：US17485119

申请日：2021-09-24

申请人： Rahul Pal ,  Dheeraj Subbareddy ,  Mahesh Kumashikar ,  Dheemanth Nagaraj ,  Rajesh Vivekanandham ,  Anshuman Thakur ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Atul Maheshwari

发明人： Rahul Pal ,  Dheeraj Subbareddy ,  Mahesh Kumashikar ,  Dheemanth Nagaraj ,  Rajesh Vivekanandham ,  Anshuman Thakur ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Atul Maheshwari

IPC分类号： H03K19/17796 ,  G06F15/78 ,  G06F30/34 ,  H03K19/17758

摘要： The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

公开(公告)号：US20210326135A1

公开(公告)日：2021-10-21

申请号：US17359039

申请日：2021-06-25

申请人： Dheeraj Subbareddy ,  Anshuman Thakur ,  Ankireddy Nalamalpu ,  MD Altaf Hossain

发明人： Dheeraj Subbareddy ,  Anshuman Thakur ,  Ankireddy Nalamalpu ,  MD Altaf Hossain

IPC分类号： G06F9/30 ,  G06F17/16

摘要： A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Specifically, a buffer of the extension architecture may be used to load data to and store data from the programmable fabric.

公开(公告)号：US20220013488A1

公开(公告)日：2022-01-13

申请号：US17484922

申请日：2021-09-24

申请人： Mahesh K. Kumashikar ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Atul Maheshwari

发明人： Mahesh K. Kumashikar ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Atul Maheshwari

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L25/00

摘要： An integrated circuit device includes multiple microbumps and a top programmable fabric die including a first programmable fabric and a first microbump interface coupled to the multiple microbumps. The integrated circuit device also includes a base programmable fabric die having a second programmable fabric and a second microbump interface coupled to the first microbump interface via a coupling to the multiple microbumps. The top programmable fabric die and the base programmable fabric die have a same design. Moreover, the top programmable fabric die and the base programmable fabric die are arranged in a three-dimensional die arrangement with the top programmable fabric die flipped above the base programmable fabric die.

公开(公告)号：US20220116041A1

公开(公告)日：2022-04-14

申请号：US17559287

申请日：2021-12-22

申请人： Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Atul Maheshwari ,  Yuet Li ,  Mahesh A. Iyer

发明人： Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Atul Maheshwari ,  Yuet Li ,  Mahesh A. Iyer

IPC分类号： H03K19/177

摘要： Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.

公开(公告)号：US20240348253A1

公开(公告)日：2024-10-17

申请号：US18757170

申请日：2024-06-27

申请人： Atul Maheshwari ,  Mahesh K. Kumashikar ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru ,  Jeffrey Christopher Chromczak

发明人： Atul Maheshwari ,  Mahesh K. Kumashikar ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru ,  Jeffrey Christopher Chromczak

IPC分类号： H03K19/17728 ,  G06F30/343 ,  H03K19/17736 ,  H03K19/17758 ,  H03K19/17796

CPC分类号： H03K19/17728 ,  G06F30/343 ,  H03K19/17744 ,  H03K19/17796 ,  H03K19/17758

摘要： Systems or methods of the present disclosure may provide an integrated circuit device that implements one region definition, which may decrease design complexity, decrease software complexity, and increase ease of use. For example, the integrated circuit device may include programmable logic that implements one region definition. The region definition may include circuitry that may implement three-dimensional (3D) input/output circuitry, 2.5D input/output circuitry, circuitry for intra-die communication, circuitry for inter-package communication, or any combination thereof. By implementing one region definition on the integrated circuit device, time spent defining each programmable logic region may be reduced or eliminated, thereby reducing design complexity software complexity associated with the integrated circuit device.

公开(公告)号：US20240346224A1

公开(公告)日：2024-10-17

申请号：US18757046

申请日：2024-06-27

申请人： Mahesh K. Kumashikar ,  Atul Maheshwari ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru

发明人： Mahesh K. Kumashikar ,  Atul Maheshwari ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru

IPC分类号： G06F30/392 ,  G06F30/33 ,  G06F119/10

CPC分类号： G06F30/392 ,  G06F30/33 ,  G06F2119/10

摘要： Systems or methods of the present disclosure may provide a multi-chip package with two or more integrated circuit devices that each include hybrid bumps. The hybrid bumps may include bumps of different sizes to facilitate different types of communication. For example, the hybrid bumps may include a first bump with fine pitch for die-to-die communication and/or a second bump with a large pitch for off-package communication. The multi-chip package may include a bridge to facilitate signal transfer between the integrated circuit device with the hybrid bumps and other components within the multi-chip package. Additionally or alternatively, the multi-chip package may include an interconnect to facilitate signal transfer between two integrated circuit devices. The interconnect may include fine pitch bumps, which may be translated by an interposer to a pitch size of the bridge. As such, the interconnect may facilitate die-to-die communication and/or off-package communication.

公开(公告)号：US20230024515A1

公开(公告)日：2023-01-26

申请号：US17957210

申请日：2022-09-30

申请人： Atul Maheshwari ,  Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Mahesh A. Iyer

发明人： Atul Maheshwari ,  Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Mahesh A. Iyer

IPC分类号： H03K19/17736 ,  H01L23/528

摘要： A programmable logic device may include a first layer formed using backside metallization on a back plane of the programmable logic device and a second fabric routing circuitry to route second data within the programmable fabric. The first layer may include first fabric routing circuitry to route first data within a programmable fabric of the programmable logic device, and clock routing circuitry to route clock signals within the programmable fabric.

公开(公告)号：US20220113788A1

公开(公告)日：2022-04-14

申请号：US17559632

申请日：2021-12-22

申请人： Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Atul Maheshwari ,  Yuet Li ,  MD Altaf Hossain

发明人： Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Atul Maheshwari ,  Yuet Li ,  MD Altaf Hossain

IPC分类号： G06F1/3287 ,  G06F30/343 ,  G06F1/324

摘要： The present disclosure describes programmable logic that may be operated in a turbo processing mode to cause an ongoing operation to be completed faster than a scheduled completion time. With at least some of the remaining time to the scheduled completion time, power savings may be realized by operating the programmable logic into a deep sleep mode, where configuration memory associated with the programmable logic may be set to a suitable voltage level as to not cause data loss at lower or zero voltage levels but otherwise realize power savings relative to an amount of power consumed during average processing operations.

公开(公告)号：US20230341463A1

公开(公告)日：2023-10-26

申请号：US18217200

申请日：2023-06-30

申请人： Kalyana Ravindra Kantipudi ,  Mahesh K. Kumashikar ,  MD Altaf Hossain ,  Ankireddy Nalamalpu

发明人： Kalyana Ravindra Kantipudi ,  Mahesh K. Kumashikar ,  MD Altaf Hossain ,  Ankireddy Nalamalpu

IPC分类号： G01R31/28 ,  G01R1/04

CPC分类号： G01R31/2896 ,  G01R1/0433

摘要： Systems and methods are provided to enable efficient testing of an integrated circuit package. Such a system may include an integrated circuit package and a testing device to test a first portion of socket pins of the integrated circuit package corresponding to a first portion of a die area using a socket during a first pass, and test a second portion of socket pins of the integrated circuit package corresponding to a second portion of the die area using the socket during a second pass.

公开(公告)号：US20190341349A1

公开(公告)日：2019-11-07

申请号：US16474005

申请日：2017-03-29

申请人： Kevin J. DORAN ,  MD Altaf HOSSAIN ,  Yu Amos ZHANG ,  Zhiguo QIAN ,  Intel Corporation

发明人： MD Altaf Hossain ,  Kevin J Doran ,  Yu Amos Zhang ,  Zhiguo Qian

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.