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公开(公告)号：US20050220297A1
公开(公告)日：2005-10-06
申请号：US11073018
申请日：2005-03-04
CPC分类号： H04L9/0668 , H04L2209/12
摘要： A bit sequence which is generated by a feedback shift register is decimated with a variable decimation value m (mε|N) in a predetermined manner which is known on the decryption side, i.e. in that every mth bit of the bit sequence is picked out from the bit sequence so as to obtain the key bit stream.
摘要翻译： 由反馈移位寄存器产生的位序列以在解密侧已知的预定方式中的可变抽取值m（mepsilon | N）被抽取，也就是说，每第m个/ 从比特序列中选出比特序列，以获得密钥比特流。
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公开(公告)号：US07764789B2
公开(公告)日：2010-07-27
申请号：US11073018
申请日：2005-03-04
CPC分类号： H04L9/0668 , H04L2209/12
摘要： A bit sequence which is generated by a feedback shift register is decimated with a variable decimation value m (mε|N) in a predetermined manner which is known on the decryption side, i.e. in that every mth bit of the bit sequence is picked out from the bit sequence so as to obtain the key bit stream.
摘要翻译： 由反馈移位寄存器产生的位序列以可解抽取值m（m＆egr | | N）以在解密侧已知的预定方式被抽取，即，比特序列的每第m位被选出 从比特序列中获取密钥比特流。
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公开(公告)号：US20090204657A1
公开(公告)日：2009-08-13
申请号：US12030648
申请日：2008-02-13
申请人： Rainer Goettfert , Stefan Rueping , Berndt Gammel
发明人： Rainer Goettfert , Stefan Rueping , Berndt Gammel
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H04L9/0861
摘要： A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently influences the PRNG, and in the second mode the TRNG and the PRNG are connected to the output via the combinational logic.
摘要翻译： 包括输出，组合逻辑，TRNG和PRNG的混合随机数发生器（HRNG）。 HRNG可配置为以第一和第二模式操作，其中在第一模式中PRNG串联连接在TRNG和输出之间，并且TRNG间歇地影响PRNG，并且在第二模式中，连接TRNG和PRNG 通过组合逻辑到输出。
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公开(公告)号：US08595277B2
公开(公告)日：2013-11-26
申请号：US12030648
申请日：2008-02-13
申请人： Rainer Goettfert , Stefan Rueping , Berndt Gammel
发明人： Rainer Goettfert , Stefan Rueping , Berndt Gammel
CPC分类号： G06F7/588 , H04L9/0861
摘要： A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently influences the PRNG, and in the second mode the TRNG and the PRNG are connected to the output via the combinational logic.
摘要翻译： 包括输出，组合逻辑，TRNG和PRNG的混合随机数发生器（HRNG）。 HRNG可配置为以第一和第二模式操作，其中在第一模式中PRNG串联连接在TRNG和输出之间，并且TRNG间歇地影响PRNG，并且在第二模式中，连接TRNG和PRNG 通过组合逻辑到输出。
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公开(公告)号：US20070033417A1
公开(公告)日：2007-02-08
申请号：US11425103
申请日：2006-06-19
申请人： Berndt Gammel , Rainer Goettfert
发明人： Berndt Gammel , Rainer Goettfert
IPC分类号： G06F12/14
CPC分类号： H03M13/2909 , G06F21/72 , H03M13/116 , H03M13/13 , H03M13/152
摘要： By arranging a redundancy means and a control means upstream from an encryption means which encrypts and decrypts the data to be stored in an external memory, the integrity of data may be ensured when the generation of redundancy information is realized by the redundancy means, and when the generation of a syndrome bit vector indicating any alteration of the data is implemented by the control means. What is preferred is a control matrix constructed from idempotent, thinly populated, circulant square sub-matrices only. By arranging redundancy and control means upstream from the encryption/decryption means, what is achieved is that both errors in the encrypted data and errors of the non-encrypted data may be proven, provided that they have occurred in the data path between the redundancy/control means and the encryption/decryption means.
摘要翻译： 通过在从存储在外部存储器中的数据进行加密和解密的加密装置的上游配置冗余装置和控制装置，当通过冗余装置实现冗余信息的生成时，可以确保数据的完整性， 通过控制装置实现表示数据的任何改变的校正子位向量的生成。 优选的是由幂等的，稀疏的，循环的方形子矩阵构成的控制矩阵。 通过从加密/解密装置上游布置冗余和控制装置，实现了加密数据中的两个错误和非加密数据的错误可以被证实，只要它们已经在冗余/ 控制装置和加密/解密装置。
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公开(公告)号：US08250659B2
公开(公告)日：2012-08-21
申请号：US11425103
申请日：2006-06-19
申请人： Berndt Gammel , Rainer Goettfert
发明人： Berndt Gammel , Rainer Goettfert
IPC分类号： G06F21/00
CPC分类号： H03M13/2909 , G06F21/72 , H03M13/116 , H03M13/13 , H03M13/152
摘要： By arranging a redundancy means and a control means upstream from an encryption means which encrypts and decrypts the data to be stored in an external memory, the integrity of data may be ensured when the generation of redundancy information is realized by the redundancy means, and when the generation of a syndrome bit vector indicating any alteration of the data is implemented by the control means. What is preferred is a control matrix constructed from idempotent, thinly populated, circulant square sub-matrices only. By arranging redundancy and control means upstream from the encryption/decryption means, what is achieved is that both errors in the encrypted data and errors of the non-encrypted data may be proven, provided that they have occurred in the data path between the redundancy/control means and the encryption/decryption means.
摘要翻译： 通过在从存储在外部存储器中的数据进行加密和解密的加密装置的上游配置冗余装置和控制装置，当通过冗余装置实现冗余信息的生成时，可以确保数据的完整性， 通过控制装置实现表示数据的任何改变的校正子位向量的生成。 优选的是从幂等的，稀疏的，循环的方形子矩阵构成的控制矩阵。 通过从加密/解密装置上游布置冗余和控制装置，实现了加密数据中的两个错误和非加密数据的错误可以被证实，只要它们已经在冗余/ 控制装置和加密/解密装置。
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7.发明授权公开(公告)号：US07979482B2
公开(公告)日：2011-07-12
申请号：US11084725
申请日：2005-03-18
申请人： Berndt Gammel , Rainer Goettfert
发明人： Berndt Gammel , Rainer Goettfert
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583
摘要： A random number generator includes a plurality of memory cells arranged in a series, a feedback processor for generating a feedback signal and for feeding the feedback signal into one of the memory cells, and a random number outputter formed to combine states of a group of at least two memory cells to obtain an output sequence. Sequences strongly differing from one another, the number of which is greater than the number of memory cells, can be generated by generating several output sequences AF0, AF1, AF2, . . . , AFk by combining states of different memory cells such that a safe and efficient bus encryption is achievable.
摘要翻译： 一种随机数发生器，包括以串联方式排列的多个存储单元，用于产生反馈信号并将反馈信号馈送到存储单元之一的反馈处理器，以及随机数输出器，其形成为将一组at 至少两个存储单元以获得输出序列。 通过产生多个输出序列AF0，AF1，AF2，可以产生彼此强度不同的序列，其数量大于存储器单元的数量。 。 。 ，AFk通过组合不同存储器单元的状态，使得可以实现安全和有效的总线加密。
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8.发明申请Device and method for determining a position of a bit error in a bit sequence 有权用于确定位序列中位错误的位置的装置和方法公开(公告)号：US20060282756A1
公开(公告)日：2006-12-14
申请号：US11383143
申请日：2006-05-12
申请人： Berndt Gammel , Rainer Goettfert , Oliver Kniffler
发明人： Berndt Gammel , Rainer Goettfert , Oliver Kniffler
CPC分类号： H03M13/19
摘要： In a device for determining a position of a bit error in a bit sequence, a check matrix is used which has a predefined number of rows and a predefined number of columns. The check matrix includes a plurality of square submatrices having a submatrix row number and a submatrix column number corresponding to the predefined number of rows or the predefined number of columns of the check matrix. The device for determining then includes a unit for receiving a bit sequence and a unit for identifying a syndrome using the check matrix and the received bit sequence. Furthermore, the device includes a unit for establishing a position of a bit error in the received bit sequence, wherein the unit for establishing is adapted to identify a syndrome bit and a syndrome bit group in the syndrome, and wherein the unit for establishing is further adapted to determine the position of the bit error in the received bit sequence using information on a position of the syndrome bit or the syndrome bit group in the syndrome, information on a relationship between the syndrome bit and the syndrome bit group, and a submatrix row number or a submatrix column number of a submatrix.
摘要翻译： 在用于确定位序列中的位错误的位置的装置中，使用具有预定数量的行和预定数量的列的校验矩阵。 校验矩阵包括具有子矩阵行号和对应于预定行数的子矩阵列号或校验矩阵的预定列数的多个正方形子矩阵。 然后，用于确定的装置包括用于接收比特序列的单元和用于使用校验矩阵和接收的比特序列来识别综合征的单元。 此外，该装置包括用于建立接收的比特序列中的比特错误的位置的单元，其中用于建立的单元适于识别该综合征中的综合征位和综合征位组，并且其中用于建立的单元进一步 适于使用关于校正子中的校正子位或校正子位组的位置的信息来确定接收到的位序列中的位错误的位置，关于校正子位和校正子位组之间的关系的信息以及子矩阵行 数字或子矩阵列号。
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公开(公告)号：US20060265604A1
公开(公告)日：2006-11-23
申请号：US11396189
申请日：2006-03-30
IPC分类号： G06F12/14
CPC分类号： H04L9/0618
摘要： An encryption unit and decryption unit located in an encryption/decryption device may be used both for encryption and decryption, without their effects canceling each other out when, between the decryption input of the decrypter and the encryption output of the encrypter. An encryption combiner maps the encryption result data block at the encryption output to a mapped encryption result data block according to an encryption combining mapping and is exemplarily used when encrypting. A decryption combiner maps the encryption result data block at the encryption output to an inversely mapped encryption result data block according to a decryption combining mapping which is inverse to the encryption combining mapping and is exemplarily used when decrypting.
摘要翻译： 位于加密/解密装置中的加密单元和解密单元既可以用于加密和解密，也可以在加密解密器的解密输入与加密器的加密输出之间进行解密，而不会影响加密/解密装置的效果。 加密组合器根据加密组合映射将加密输出处的加密结果数据块映射到映射的加密结果数据块，并且在加密时被示例性地使用。 解密组合器根据与加密组合映射相反的解密组合映射将加密输出处的加密结果数据块映射到反映射的加密结果数据块，并且在解密时被示例性地使用。
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公开(公告)号：US08861725B2
公开(公告)日：2014-10-14
申请号：US13545587
申请日：2012-07-10
申请人： Rainer Goettfert , Berndt Gammel , Markus Gail , Wieland Fischer
发明人： Rainer Goettfert , Berndt Gammel , Markus Gail , Wieland Fischer
CPC分类号： H04L9/0662 , G06F7/58 , H04L9/0668
摘要： A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.
摘要翻译： 随机比特流生成器包括多个反馈移位寄存器，其被配置为存储表示随机比特流生成器的内部状态的多个比特值。 每个反馈移位寄存器包括寄存器输入和寄存器输出。 随机比特流生成器还包括布尔输出功能，其被配置为从多个反馈寄存器接收多个寄存器输出，以执行多个寄存器输出的第一布尔组合，并提供相应的输出位，其中多个 的连续输出位形成随机比特流。 反馈回路被配置为执行输出位与至少一个反馈移位寄存器的至少一个寄存器反馈位的第二布尔组合，使得至少一个反馈移位寄存器的寄存器输入是 输出位。
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