-
1.发明申请公开(公告)号：US20080125985A1
公开(公告)日：2008-05-29
申请号：US11530100
申请日：2006-09-08
CPC分类号： G06F17/5036
摘要： First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 第一硬件是用于响应于描述集成电路的宏执行第一软件，以及响应于第一软件的执行而产生一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
-
2.发明申请公开(公告)号：US20110072406A1
公开(公告)日：2011-03-24
申请号：US12957881
申请日：2010-12-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
-
3.发明授权公开(公告)号：US08370780B2
公开(公告)日：2013-02-05
申请号：US12957881
申请日：2010-12-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
-
公开(公告)号：US07913201B2
公开(公告)日：2011-03-22
申请号：US12130644
申请日：2008-05-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
-
公开(公告)号：US20080288910A1
公开(公告)日：2008-11-20
申请号：US12130644
申请日：2008-05-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
-
6.发明授权公开(公告)号：US07720667B2
公开(公告)日：2010-05-18
申请号：US11530100
申请日：2006-09-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 第一硬件是用于响应于描述集成电路的宏执行第一软件，以及响应于第一软件的执行而产生一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
-
7.发明授权Method for optimizing power in a very large scale integration (VLSI) design by detecting clock gating opportunities 失效通过检测时钟门控机会来优化大规模集成（VLSI）设计中的功率的方法公开(公告)号：US07509606B2
公开(公告)日：2009-03-24
申请号：US11380126
申请日：2006-04-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A computer implemented power optimization method that generates statistics relating to the clock gating of a set of components in a VLSI design. A set of components, including those components which are not clock gated, are identified. The generation of statistics related to clock gating testing identify whether one or more components of the set of components may be clock gated.
摘要翻译： 一种计算机实现的功率优化方法，其生成与VLSI设计中的一组组件的时钟门控相关的统计信息。 识别一组组件，包括不是时钟门控的组件。 与时钟门控测试相关的统计信息的生成识别组件组中的一个或多个组件是否可以是时钟门控。
-
8.发明申请METHOD AND APPARATUS IN LOCATING CLOCK GATING OPPORTUNITIES WITHIN A VERY LARGE SCALE INTEGRATION CHIP DESIGN 失效在非常大的规模集成芯片设计中定位时钟机会的方法和设备公开(公告)号：US20070250798A1
公开(公告)日：2007-10-25
申请号：US11380126
申请日：2006-04-25
申请人： RAJAT CHAUDHRY , Tilman Gloekler , Daniel Stasiak , Todd Swanson
发明人： RAJAT CHAUDHRY , Tilman Gloekler , Daniel Stasiak , Todd Swanson
CPC分类号： G06F17/5031
摘要： A computer implemented method, apparatus, and computer usable program code for generating statistics for a set of components in a computer chip. An exemplary computer implemented method includes identifying the set of components in the computer chip. The set of components include those components which are not clock gated. The exemplary method also includes generating statistics for the set of components. The statistics are related to clock gating testing to identify whether one or more components of the set of components can be clock gated.
摘要翻译： 一种计算机实现的方法，装置和计算机可用程序代码，用于生成计算机芯片中的一组组件的统计。 示例性的计算机实现的方法包括识别计算机芯片中的组件集合。 这些组件包括不是时钟门控的组件。 该示例性方法还包括生成该组组件的统计信息。 这些统计信息与时钟门控测试相关，以确定组件组中的一个或多个组件是否可以进行时钟门控。
-
公开(公告)号：US20080167853A1
公开(公告)日：2008-07-10
申请号：US11621361
申请日：2007-01-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/31704 , G01R31/318357 , G06F11/261
摘要： A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns
摘要翻译： 提供通用计算资源用于执行系统的通用操作。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件
-
公开(公告)号：US20080288230A1
公开(公告)日：2008-11-20
申请号：US12130675
申请日：2008-05-30
IPC分类号： G06F17/50
CPC分类号： G01R31/31704 , G01R31/318357 , G06F17/5022
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括用于执行系统的通用操作的通用计算资源。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。
-
-
-
-
-
-
-
-
-
搜索结果
53 条记录 (耗时 0.03 秒)
