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1.发明申请公开(公告)号：US20110072406A1
公开(公告)日：2011-03-24
申请号：US12957881
申请日：2010-12-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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公开(公告)号：US07605612B1
公开(公告)日：2009-10-20
申请号：US12121827
申请日：2008-05-16
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Daniel L. Stasiak , Albert J. Van Norstrand, Jr.
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Daniel L. Stasiak , Albert J. Van Norstrand, Jr.
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , G06F1/3203 , G06F1/3237 , G06F17/505 , G06F2217/78 , G06F2217/84 , Y02D10/128
摘要： A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value. Based on a current state of the control state machine, a load signal is provided to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register.
摘要翻译： 时钟选通集成电路的时钟域的技术包括将第一，第二和第三值存储在控制寄存器中。 第一值对应于在启动时钟门控之前等待的第一数量的时钟周期，第二值对应于执行时钟门控的第二数量的时钟周期，并且第三值对应于第三数量的时钟周期，其中 不执行时钟门控。 第一，第二和第三值之一被选择性地从控制寄存器加载到计数电路中。 计数电路从加载的第一，第二和第三值之一计数到转换值。 在控制状态机（从计数电路）接收到比较信号，指示计数电路已经达到转换值。 基于控制状态机的当前状态，向计数电路提供负载信号，使得计数电路从控制寄存器加载相关的第一，第二和第三值中的一个。
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3.发明申请Distributing Integrated Circuit Net Power Accurately in Power and Thermal Analysis 失效在功率和热分析中精确分配集成电路净功率公开(公告)号：US20090132834A1
公开(公告)日：2009-05-21
申请号：US11942030
申请日：2007-11-19
IPC分类号： G06F1/26
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/78 , G06F2217/80
摘要： A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.
摘要翻译： 提供了一种准确分配净功率的方法，系统和计算机程序产品。 在集成电路上模拟工作负载。 为集成电路中的一组网络和一组子网确定净交换活动。 基于净交换活动生成净交换数据。 使用净交换数据和每个单独网络或子网的净电容，为每个单独的网络和每个单独的子网计算净功率值。 每个计算的净功率值被分配给驱动单个网络或子网的一组源设备中的一个，其中净功率被精确地分配。 基于将每个净功率值分配给驱动单个网络或子网的一组源设备中的一个，生成净功率分配列表。
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4.发明授权公开(公告)号：US07720667B2
公开(公告)日：2010-05-18
申请号：US11530100
申请日：2006-09-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 第一硬件是用于响应于描述集成电路的宏执行第一软件，以及响应于第一软件的执行而产生一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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5.发明申请公开(公告)号：US20090295402A1
公开(公告)日：2009-12-03
申请号：US12131476
申请日：2008-06-02
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.
摘要翻译： 提供了一种表征具有至少一个电压岛和至少一个性能屏幕环形振荡器（PSRO）的芯片的性能的方法。 片上性能监视器（OCPM）被并入电压岛。 电压岛的性能测量仅在电源岛上产生。 性能屏幕环形振荡器（PSRO）的性能测量仅在电源电压岛下产生。 将性能屏幕环形振荡器（PSRO）的性能测量与片内性能监视器（OCPM）的性能测量进行比较，以确定由于电压岛引起的系统偏移。 使用由于电压岛引起的系统偏移来调整性能模型。
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6.发明授权公开(公告)号：US08020138B2
公开(公告)日：2011-09-13
申请号：US12131476
申请日：2008-06-02
IPC分类号： G06F17/50
CPC分类号： G01R31/2884
摘要： A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.
摘要翻译： 提供了一种表征具有至少一个电压岛和至少一个性能屏幕环形振荡器（PSRO）的芯片的性能的方法。 片上性能监视器（OCPM）被并入电压岛。 电压岛的性能测量仅在电源岛上产生。 性能屏幕环形振荡器（PSRO）的性能测量仅在电源电压岛下产生。 将性能屏幕环形振荡器（PSRO）的性能测量与片内性能监视器（OCPM）的性能测量进行比较，以确定由于电压岛引起的系统偏移。 使用由于电压岛引起的系统偏移来调整性能模型。
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7.发明申请公开(公告)号：US20080125985A1
公开(公告)日：2008-05-29
申请号：US11530100
申请日：2006-09-08
CPC分类号： G06F17/5036
摘要： First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 第一硬件是用于响应于描述集成电路的宏执行第一软件，以及响应于第一软件的执行而产生一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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公开(公告)号：US07058131B2
公开(公告)日：2006-06-06
申请号：US10007191
申请日：2001-11-08
CPC分类号： H04L25/0298 , H04L1/242 , H04L7/0008 , H04L25/0272 , H04L25/028 , H04L25/0292
摘要： A high speed signal transmission system employs differential receivers for receiving data signals transmitted over circuit transmission lines. One input each receiver is coupled to the output of a transmission line and to a termination network. The termination network generates a termination voltage and a source impedance that is matched to the characteristic impedance of the transmission line. The other input of the receiver is coupled to a reference voltage. The termination voltage may be adjusted by programming signals while keeping the source impedance constant and matched to the transmission line. A test mode may be employed where known data signals are transmitted and received and the termination voltage is adjusted while monitoring the states of the received signals on the output of the receivers. In this manner, the system may be optimized or tested for noise margin in an actual operation environment without resorting to probing methods. The clock signal used to time the transmission of the data signals is likewise transmitted along with its complement on two additional transmission lines. The clock signals are received in termination networks like the data signals. Additionally, the two clock signals are coupled to the reference signal with resistor/capacitor filter networks generating a low frequency tracking voltage superimposed on the reference voltage further improving noise margins.
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公开(公告)号：US4941120A
公开(公告)日：1990-07-10
申请号：US339347
申请日：1989-04-17
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/49947
摘要： Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.
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10.发明授权
公开(公告)号：US4926370A
公开(公告)日：1990-05-15
申请号：US339348
申请日：1989-04-17
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/49957
摘要： A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalized circuit and a round circuit, and the first two bit positions of the fractional result are examined. If the 2-bit format is 1.X the round circuit is activated; if the 2-bit format is 0.1X the fractional result is shifted left one position and the round circuit is activated; if the 2-bit format is in neither of the above formats the normalize circuit is activated. In no event is it necessary to activate sequentially the normalize circuit and the round circuit.
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