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1.发明申请公开(公告)号：US20110072406A1
公开(公告)日：2011-03-24
申请号：US12957881
申请日：2010-12-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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2.发明申请Distributing Integrated Circuit Net Power Accurately in Power and Thermal Analysis 失效在功率和热分析中精确分配集成电路净功率公开(公告)号：US20090132834A1
公开(公告)日：2009-05-21
申请号：US11942030
申请日：2007-11-19
IPC分类号： G06F1/26
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/78 , G06F2217/80
摘要： A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.
摘要翻译： 提供了一种准确分配净功率的方法，系统和计算机程序产品。 在集成电路上模拟工作负载。 为集成电路中的一组网络和一组子网确定净交换活动。 基于净交换活动生成净交换数据。 使用净交换数据和每个单独网络或子网的净电容，为每个单独的网络和每个单独的子网计算净功率值。 每个计算的净功率值被分配给驱动单个网络或子网的一组源设备中的一个，其中净功率被精确地分配。 基于将每个净功率值分配给驱动单个网络或子网的一组源设备中的一个，生成净功率分配列表。
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3.发明授权Method and apparatus to generate circuit energy models with multiple clock gating inputs 失效用多个时钟门控输入产生电路能量模型的方法和装置公开(公告)号：US07343499B2
公开(公告)日：2008-03-11
申请号：US11044568
申请日：2005-01-27
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.
摘要翻译： 提供了一种方法，计算机程序和装置，用于使用多个时钟选通输入来产生用于宏的电路能量模型。 电路能量模型用于估计系统功耗。 本发明使得能够为包含多个时钟选通输入的宏创建电路能量模型。 能量表基于宏的输入开关因子和时钟激活百分比创建。 通过在模拟期间打开和关闭多个时钟门控输入来产生时钟激活百分比。 这些能量表是从最小数量的功率模拟产生的。 通过使用时钟激活百分比作为参数，产生精确的功率估计。
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4.发明申请Method and apparatus to generate circuit energy models with multiple clock gating inputs 失效用多个时钟门控输入产生电路能量模型的方法和装置公开(公告)号：US20060168456A1
公开(公告)日：2006-07-27
申请号：US11044568
申请日：2005-01-27
申请人： Rajat Chaudhry , James Neely , Daniel Stasiak
发明人： Rajat Chaudhry , James Neely , Daniel Stasiak
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.
摘要翻译： 提供了一种方法，计算机程序和装置，用于使用多个时钟选通输入来产生用于宏的电路能量模型。 电路能量模型用于估计系统功耗。 本发明使得能够为包含多个时钟选通输入的宏创建电路能量模型。 能量表基于宏的输入开关因子和时钟激活百分比创建。 通过在模拟期间打开和关闭多个时钟门控输入来产生时钟激活百分比。 这些能量表是从最小数量的功率模拟产生的。 通过使用时钟激活百分比作为参数，产生精确的功率估计。
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5.发明申请公开(公告)号：US20060190856A1
公开(公告)日：2006-08-24
申请号：US11044597
申请日：2005-01-27
申请人： Rajat Chaudhry , James Neely , Daniel Stasiak
发明人： Rajat Chaudhry , James Neely , Daniel Stasiak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain clock gating inputs. Power tables are created based upon the macro's input switching factor percentage and the clock activation percentage. These power tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate energy tables are produced.
摘要翻译： 提供了一种方法，计算机程序和装置，用于使用时钟门控输入来产生用于宏的电路能量模型。 电路能量模型用于估计系统功耗。 本发明使得能够为包含时钟门控输入的宏创建电路能量模型。 功率表基于宏的输入开关因子百分比和时钟激活百分比创建。 这些功率表是从最小数量的功率模拟产生的。 通过使用时钟激活百分比作为参数，产生精确的能量表。
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公开(公告)号：US20050278664A1
公开(公告)日：2005-12-15
申请号：US10855725
申请日：2004-05-27
申请人： Rajat Chaudhry , Sang Dhong , Stephen Posluszny , Daniel Stasiak
发明人： Rajat Chaudhry , Sang Dhong , Stephen Posluszny , Daniel Stasiak
CPC分类号： G06F17/5022
摘要： A method, an apparatus, and a computer program are provided for predicting power consumption for chip. The model for predicting power consumptions is modified so at to provide a high degree of accuracy with a minimal amount of computing time. Traditionally, when modeling a chip, a vast amount of time and computer resources were required to predict power consumption. Techniques required less time and less computer power, but the accuracy also decreased. However, by breaking down a chip into macros and developing energy rules for each macro, simple techniques can be employed to accurately predict power consumption under real world conditions with a minimal amount of time and computing power.
摘要翻译： 提供了一种用于预测芯片功耗的方法，装置和计算机程序。 修改用于预测功耗的模型，以便以最小的计算时间提供高精度。 传统上，当对芯片建模时，需要大量的时间和计算机资源来预测功耗。 技术需要更少的时间和更少的计算机功率，但精度也降低了。 然而，通过将芯片分解成宏并为每个宏开发能量规则，可以采用简单的技术来以最小的时间和计算能力精确地预测现实世界条件下的功耗。
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7.发明授权Method and apparatus for controlling current demand in an integrated circuit 有权用于控制集成电路中的电流需求的方法和装置公开(公告)号：US06819538B2
公开(公告)日：2004-11-16
申请号：US09858126
申请日：2001-05-15
申请人： David T. Blaauw , Rajendran V. Panda , Rajat Chaudhry , Vladimir P. Zolotov , Ravindraraj Ramaraju
发明人： David T. Blaauw , Rajendran V. Panda , Rajat Chaudhry , Vladimir P. Zolotov , Ravindraraj Ramaraju
IPC分类号： H02H300
CPC分类号： G06F1/305
摘要： The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.
摘要翻译： 本发明一般涉及用于控制集成电路中的电流需求的方法和装置。 一个实施例涉及一种方法，其包括检测是否存在电源电压过冲或下冲，并且如果检测到的话，控制消耗电力消耗的电流以确保电源电压保持在可接受的水平内。 其他实施例涉及具有电容去耦结构，功耗电路和功耗控制电路的集成电路，用于控制由功耗电路的至少一部分消耗的电流。 因此，本发明的实施例涉及监视和控制功耗电路（例如集成电路）的功耗（即电流需求），以便防止毁坏性的电源电压欠冲，过冲和振荡。
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8.发明授权Method and apparatus to generate circuit energy models with multiple clock gating inputs 失效用多个时钟门控输入产生电路能量模型的方法和装置公开(公告)号：US07725744B2
公开(公告)日：2010-05-25
申请号：US12016706
申请日：2008-01-18
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.
摘要翻译： 提供了一种方法，计算机程序和装置，用于使用多个时钟选通输入来产生用于宏的电路能量模型。 电路能量模型用于估计系统功耗。 本发明使得能够为包含多个时钟选通输入的宏创建电路能量模型。 能量表基于宏的输入开关因子和时钟激活百分比创建。 通过在模拟期间打开和关闭多个时钟门控输入来产生时钟激活百分比。 这些能量表是从最小数量的功率模拟产生的。 通过使用时钟激活百分比作为参数，产生精确的功率估计。
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9.发明授权公开(公告)号：US07720667B2
公开(公告)日：2010-05-18
申请号：US11530100
申请日：2006-09-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 第一硬件是用于响应于描述集成电路的宏执行第一软件，以及响应于第一软件的执行而产生一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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10.发明申请METHOD FOR PERFORMING POWER SIMULATIONS ON COMPLEX DESIGNS RUNNING COMPLEX SOFTWARE APPLICATIONS 审中-公开复杂设计运行复杂软件应用的电源仿真方法公开(公告)号：US20080021692A1
公开(公告)日：2008-01-24
申请号：US11459060
申请日：2006-07-21
申请人： Rajat Chaudhry , Sang H. Dhong , Gilles Gervais , Danny J. Klema
发明人： Rajat Chaudhry , Sang H. Dhong , Gilles Gervais , Danny J. Klema
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F1/3203 , G06F2217/78 , Y02D10/124
摘要： A power estimation system uses a hardware accelerated simulator to advance simulation to a point of interest for power estimation. The hardware accelerated simulator generates a checkpoint file, which is then used by a software simulator to initiate simulation of the processor design model for power estimation. An on-the-fly power estimator provides power calculations in memory. Thus, the power estimation system described herein isolates instruction sequences to determine portions of software code that may consume excess power or generate noise and to provide a more accurate power estimate on the fly.
摘要翻译： 功率估计系统使用硬件加速模拟器将模拟推进到功率估计的兴趣点。 硬件加速模拟器产生一个检查点文件，然后由软件模拟器用来启动用于功率估计的处理器设计模型的仿真。 动态功率估计器在存储器中提供功率计算。 因此，本文描述的功率估计系统隔离指令序列以确定可消耗过多功率或产生噪声的软件代码的部分并且在飞行中提供更准确的功率估计。
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