-
公开(公告)号：US09946550B2
公开(公告)日：2018-04-17
申请号：US11856170
申请日：2007-09-17
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/30094 , G06F9/384
摘要： A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.
-
公开(公告)号：US20090077354A1
公开(公告)日：2009-03-19
申请号：US11856170
申请日：2007-09-17
IPC分类号： G06F9/318
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/30094 , G06F9/384
摘要： A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.
摘要翻译： 用于处理无序处理器中的预定代码的技术包括检测与预定代码区相关联的谓词定义指令。 然后，在预定的代码区域内重命名预定的指令，直到谓词定义指令的谓词解决为止。
-
3.发明申请公开(公告)号：US20090288063A1
公开(公告)日：2009-11-19
申请号：US12123083
申请日：2008-05-19
申请人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4451
摘要： A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
摘要翻译： 用于无序指令处理的预测技术提供了低硬件开销的有效的无序执行。 一个特殊的操作代码区分了程序代码的统一区域，其中包含依赖于条件分辨率的预测指令。 与特殊操作码相关联的字段或操作数指示操作码后面的指令数，并且还包含每个指令与其对应条件路径的关联的指示。 区域中的每个条件寄存器写入对于每个条件路径都有相应的寄存器写入，如果对称性尚未存在，编译器插入附加的寄存器写入，形成一组寄存器写操作。 因此，统一的指令流可以使用与相同重名资源相关联的寄存器写入进行解码和分派，并且通过执行由解析条件指定的特定指令来解决条件寄存器写入。
-
4.发明申请PREDICATION SUPPORT IN AN OUT-OF-ORDER PROCESSOR BY SELECTIVELY EXECUTING AMBIGUOUSLY RENAMED WRITE OPERATIONS 有权通过选择性地执行经过复制的写作操作，在订单处理程序中进行预测支持公开(公告)号：US20090287908A1
公开(公告)日：2009-11-19
申请号：US12123046
申请日：2008-05-19
申请人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F8/441 , G06F9/3005 , G06F9/30072 , G06F9/3842 , G06F9/3885
摘要： A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
摘要翻译： 用于无序指令处理的预测技术提供了低硬件开销的有效的无序执行。 一个特殊的操作代码区分了程序代码的统一区域，其中包含依赖于条件分辨率的预测指令。 与特殊操作码相关联的字段或操作数指示操作码后面的指令数，并且还包含每个指令与其对应条件路径的关联的指示。 区域中的每个条件寄存器写入对于每个条件路径都有相应的寄存器写入，如果对称性尚未存在，编译器插入附加的寄存器写入，形成一组寄存器写操作。 因此，统一的指令流可以使用与相同重名资源相关联的寄存器写入进行解码和分派，并且通过执行由解析条件指定的特定指令来解决条件寄存器写入。
-
5.发明授权Predication support in an out-of-order processor by selectively executing ambiguously renamed write operations 有权通过选择性地执行模糊的重命名写操作，在无序处理器中进行预测支持公开(公告)号：US07886132B2
公开(公告)日：2011-02-08
申请号：US12123046
申请日：2008-05-19
申请人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
CPC分类号： G06F9/384 , G06F8/441 , G06F9/3005 , G06F9/30072 , G06F9/3842 , G06F9/3885
摘要： A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
摘要翻译： 用于无序指令处理的预测技术提供了低硬件开销的有效的无序执行。 一个特殊的操作代码区分了程序代码的统一区域，其中包含依赖于条件分辨率的预测指令。 与特殊操作码相关联的字段或操作数指示操作码后面的指令数，并且还包含每个指令与其对应条件路径的关联的指示。 区域中的每个条件寄存器写入对于每个条件路径都有相应的寄存器写入，如果对称性尚未存在，编译器插入附加的寄存器写入，形成一组寄存器写操作。 因此，统一的指令流可以使用与相同重名资源相关联的寄存器写入进行解码和分派，并且通过执行由解析条件指定的特定指令来解决条件寄存器写入。
-
6.发明授权Predication supporting code generation by indicating path associations of symmetrically placed write instructions 有权通过指示对称放置的写指令的路径关联来支持代码生成的预测公开(公告)号：US09262140B2
公开(公告)日：2016-02-16
申请号：US12123083
申请日：2008-05-19
申请人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4451
摘要： A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
摘要翻译： 用于无序指令处理的预测技术提供了低硬件开销的有效的无序执行。 一个特殊的操作代码区分了程序代码的统一区域，其中包含依赖于条件分辨率的预测指令。 与特殊操作码相关联的字段或操作数指示操作码后面的指令数，并且还包含每个指令与其对应条件路径的关联的指示。 区域中的每个条件寄存器写入对于每个条件路径都有相应的寄存器写入，如果对称性尚未存在，编译器插入附加的寄存器写入，形成一组寄存器写操作。 因此，统一的指令流可以使用与相同重名资源相关联的寄存器写入进行解码和分派，并且通过执行由解析条件指定的特定指令来解决条件寄存器写入。
-
7.发明申请公开(公告)号：US20090271772A1
公开(公告)日：2009-10-29
申请号：US12108556
申请日：2008-04-24
申请人： Mark W. Stephenson , Ram Rangan
发明人： Mark W. Stephenson , Ram Rangan
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： A method, computer system, and computer program product for using one or more hardware interrupts to drive dynamic binary code recompilation. The execution of a plurality of instructions is monitored to detect a problematic instruction. In response to detecting the problematic instruction, a hardware interrupt is thrown to a dynamic interrupt handler. A determination is made whether a threshold for dynamic binary code recompilation is satisfied. If the threshold for dynamic code recompilation is satisfied, the dynamic interrupt handler optimizes at least one of the plurality of instructions.
摘要翻译： 一种用于使用一个或多个硬件中断来驱动动态二进制代码重新编译的方法，计算机系统和计算机程序产品。 监视多个指令的执行以检测有问题的指令。 响应于检测到有问题的指令，硬件中断被抛出到动态中断处理程序。 确定是否满足动态二进制代码重新编译的阈值。 如果满足动态代码重新编译的阈值，则动态中断处理程序优化多个指令中的至少一个。
-
公开(公告)号：US08453129B2
公开(公告)日：2013-05-28
申请号：US12108556
申请日：2008-04-24
申请人： Mark W. Stephenson , Ram Rangan
发明人： Mark W. Stephenson , Ram Rangan
IPC分类号： G06F9/45
CPC分类号： G06F9/45516
摘要： A method, computer system, and computer program product for using one or more hardware interrupts to drive dynamic binary code recompilation. The execution of a plurality of instructions is monitored to detect a problematic instruction. In response to detecting the problematic instruction, a hardware interrupt is thrown to a dynamic interrupt handler. A determination is made whether a threshold for dynamic binary code recompilation is satisfied. If the threshold for dynamic code recompilation is satisfied, the dynamic interrupt handler optimizes at least one of the plurality of instructions.
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.02 秒)
