公开(公告)号：US12027197B2

公开(公告)日：2024-07-02

申请号：US17309770

申请日：2019-12-11

Applicant: Rambus Inc.

Inventor： Shahram Nikoukary ,  Jonghyun Cho ,  Anand Jai ,  Pradeep Batra ,  Lei Luo

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/22 ,  G11C7/222

Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.