公开(公告)号：US12027197B2

公开(公告)日：2024-07-02

申请号：US17309770

申请日：2019-12-11

Applicant: Rambus Inc.

Inventor： Shahram Nikoukary ,  Jonghyun Cho ,  Anand Jai ,  Pradeep Batra ,  Lei Luo

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/22 ,  G11C7/222

Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

公开(公告)号：US11742277B2

公开(公告)日：2023-08-29

申请号：US17264231

申请日：2019-08-12

Applicant: Rambus Inc.

Inventor： Shahram Nikoukary ,  Jonghyun Cho ,  Nitin Juneja ,  Ming Li

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816

Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

公开(公告)号：US12211583B2

公开(公告)日：2025-01-28

申请号：US18021442

申请日：2021-08-24

Applicant: Rambus Inc.

Inventor： Torsten Partsch ,  Shahram Nikoukary ,  Catherine Chen

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/22

Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.

公开(公告)号：US12087681B2

公开(公告)日：2024-09-10

申请号：US18218280

申请日：2023-07-05

Applicant: Rambus Inc.

Inventor： Shahram Nikoukary ,  Jonghyun Cho ,  Nitin Juneja ,  Ming Li

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816

Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

公开(公告)号：US20230298642A1

公开(公告)日：2023-09-21

申请号：US18021442

申请日：2021-08-24

Applicant: Rambus Inc.

Inventor： Torsten Partsch ,  Shahram Nikoukary ,  Catherine Chen

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1084 ,  G11C7/1057 ,  G11C7/222

Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.

公开(公告)号：US12237258B2

公开(公告)日：2025-02-25

申请号：US17608725

申请日：2020-04-30

Applicant: Rambus Inc.

Inventor： Shahram Nikoukary ,  Dongwoo Hong ,  Jonghyun Cho

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H03K19/003 ,  H04B15/02 ,  H01L23/66

Abstract: The embodiments herein are directed to technologies for crosstalk cancellation structures. One semiconductor package includes conductive metal layers separated by insulating layers, the conductive metal layers for routing signals between external package terminals and pads on an integrated circuit device. Signal lines formed in the conductive metal layers have electrode structure (capacitor electrode-like structures) formed for at least adjacent signaling lines of the package terminals. Two of the electrode structures from the adjacent signaling lines are formed opposite each other on different metal layers.

公开(公告)号：US20220319980A1

公开(公告)日：2022-10-06

申请号：US17608725

申请日：2020-04-30

Applicant: Rambus Inc.

Inventor： Shahram Nikoukary ,  Dongwoo Hong ,  Jonghyun Cho

IPC: H01L23/522 ,  H03K19/003 ,  H04B15/02 ,  H01L23/498 ,  H01L23/528

Abstract: The embodiments herein are directed to technologies for crosstalk cancellation structures. One semiconductor package includes conductive metal layers separated by insulating layers, the conductive metal layers for routing signals between external package terminals and pads on an integrated circuit device. Signal lines formed in the conductive metal layers have electrode structure (capacitor electrode-like structures) formed for at least adjacent signaling lines of the package terminals. Two of the electrode structures from the adjacent signaling lines are formed opposite each other on different metal layers.