公开(公告)号：US20240361958A1

公开(公告)日：2024-10-31

申请号：US18663319

申请日：2024-05-14

Applicant: Rambus Inc.

Inventor： Frederick WARE

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0683 ,  G06F12/06 ,  G06F13/1689 ,  G06F13/4086 ,  G06F13/4256 ,  G06F13/1684

Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

公开(公告)号：US20230266923A1

公开(公告)日：2023-08-24

申请号：US18121231

申请日：2023-03-14

Applicant: Rambus Inc.

Inventor： Frederick WARE

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F12/06 ,  G06F13/4086 ,  G06F13/1689 ,  G06F13/4256 ,  G06F13/1684

Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

公开(公告)号：US20220147478A1

公开(公告)日：2022-05-12

申请号：US17521399

申请日：2021-11-08

Applicant: Rambus Inc.

Inventor： Frederick WARE

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.