公开(公告)号：US20170206168A1

公开(公告)日：2017-07-20

申请号：US15393232

申请日：2016-12-28

Applicant: RAMBUS INC.

Inventor： Trung DIEP ,  Hongzhong ZHENG

IPC: G06F12/1009 ,  G06F12/0811

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/0864 ,  G06F2212/283 ,  G06F2212/656 ,  G11C7/1072

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

公开(公告)号：US20240273038A1

公开(公告)日：2024-08-15

申请号：US18586867

申请日：2024-02-26

Applicant: Rambus Inc.

Inventor： Hongzhong ZHENG ,  Brent Haukness

IPC: G06F13/16 ,  G06F5/14

CPC classification number: G06F13/1626 ,  G06F5/14

Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

公开(公告)号：US20220391332A1

公开(公告)日：2022-12-08

申请号：US17852135

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Hongzhong ZHENG ,  Brent HAUKNESS

IPC: G06F13/16 ,  G06F5/14

Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

公开(公告)号：US20200334009A1

公开(公告)日：2020-10-22

申请号：US16872681

申请日：2020-05-12

Applicant: Rambus Inc.

Inventor： Hongzhong ZHENG ,  Brent HAUKNESS

IPC: G06F5/14 ,  G06F13/16

Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.