公开(公告)号：US12211540B2

公开(公告)日：2025-01-28

申请号：US18399096

申请日：2023-12-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F12/00 ,  G06F13/16 ,  G11C11/406

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

公开(公告)号：US20240054084A1

公开(公告)日：2024-02-15

申请号：US18239681

申请日：2023-08-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F13/16

CPC classification number: G06F13/1689

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

公开(公告)号：US09715424B1

公开(公告)日：2017-07-25

申请号：US14458546

申请日：2014-08-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G01R31/28 ,  G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F12/02

CPC classification number: G06F11/1008 ,  G06F11/1048 ,  G06F12/0246 ,  G11C29/52

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

公开(公告)号：US20160019962A1

公开(公告)日：2016-01-21

申请号：US14866920

申请日：2015-09-26

Applicant: Rambus Inc.

Inventor： Brent Haukness

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C8/08 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/79

Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.

公开(公告)号：US09153321B2

公开(公告)日：2015-10-06

申请号：US14483359

申请日：2014-09-11

Applicant: Rambus Inc.

Inventor： Brent Haukness

IPC: G11C13/00 ,  G11C8/08

CPC classification number: G11C13/0069 ,  G11C8/08 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/79

Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.

Abstract translation: 1晶体管1电阻（1T1R）型RRAM单元的存取晶体管的栅极使用电流镜相对于存取晶体管的源极偏置。 在跨过1T1R单元（例如经由位线）施加的电压的影响下，RRAM存储元件从较高的电阻切换到较低的电阻。 当RRAM存储元件从较高的电阻切换到较低电阻时，通过RRAM单元的电流基本上由RRAM器件的较高电阻（而存取晶体管在线性区域中工作）基本确定为基本确定 通过存取晶体管的饱和区工作点。

公开(公告)号：US09007862B2

公开(公告)日：2015-04-14

申请号：US13938130

申请日：2013-07-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness ,  Ian P. Shaeffer ,  James E. Harris

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

CPC classification number: G11C7/00 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40622

Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

Abstract translation: 诸如存储器控制器和存储器设备的存储器系统的组件通过控制存储器件的刷新定时来减少退出自刷新模式的延迟。 存储器件包括存储器核。 存储装置的接口电路接收指示间歇刷新事件的外部刷新信号。 存储器件的刷新电路产生指示存储器件的内部刷新事件的内部刷新信号。 存储器件的刷新控制电路响应于内部刷新事件，在相对于由外部刷新信号指示的间歇刷新事件的时间，对存储器核心的一部分执行刷新操作。

公开(公告)号：US11755509B2

公开(公告)日：2023-09-12

申请号：US17715404

申请日：2022-04-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F13/16

CPC classification number: G06F13/1689

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

公开(公告)号：US11314669B2

公开(公告)日：2022-04-26

申请号：US16660768

申请日：2019-10-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F13/16

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

公开(公告)号：US10892001B2

公开(公告)日：2021-01-12

申请号：US16692069

申请日：2019-11-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F12/00 ,  G11C11/406 ,  G06F13/16

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

公开(公告)号：US20180122471A1

公开(公告)日：2018-05-03

申请号：US15790312

申请日：2017-10-23

Applicant: Rambus Inc.

Inventor： Brent Haukness

IPC: G11C13/00 ,  G11C8/08

CPC classification number: G11C13/0069 ,  G11C8/08 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/79

Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.