公开(公告)号：US11705903B2

公开(公告)日：2023-07-18

申请号：US17526830

申请日：2021-11-15

Applicant: Rambus Inc.

Inventor： Alain Rousson ,  Hui Song ,  Ravi Shivnaraine ,  Christopher Holdenried ,  Hector Villacorta

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0027 ,  H03K19/01855 ,  H03K19/018521

Abstract: The embodiments herein describe technologies for back-gate biasing of clock trees using a reference generator. A circuit includes a set of clock buffers and a programmable voltage reference generator to apply a voltage to a back gate of a transistor of the set of clock buffers.

公开(公告)号：US20220158637A1

公开(公告)日：2022-05-19

申请号：US17526830

申请日：2021-11-15

Applicant: Rambus Inc.

Inventor： Alain Rousson ,  Hui Song ,  Ravi Shivnaraine ,  Christopher Holdenried ,  Hector Villacorta

IPC: H03K19/00 ,  H03K19/0185

Abstract: The embodiments herein describe technologies for back-gate biasing of clock trees using a reference generator. A circuit includes a set of clock buffers and a programmable voltage reference generator to apply a voltage to a back gate of a transistor of the set of clock buffers.