公开(公告)号：US11782476B2

公开(公告)日：2023-10-10

申请号：US17529515

申请日：2021-11-18

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Marcial Chua ,  Srinivas Satish Babu Bamdhamravuri ,  Abhishek Desai ,  Philip Lu ,  Cosmin Iorga

IPC: G06F1/10

CPC classification number: G06F1/10

Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

公开(公告)号：US20220179444A1

公开(公告)日：2022-06-09

申请号：US17529515

申请日：2021-11-18

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Marcial Chua ,  Srinivas Satish Babu Bamdhamravuri ,  Abhishek Desai ,  Philip Lu ,  Cosmin Iorga

IPC: G06F1/10

Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.