公开(公告)号：US20240055068A1

公开(公告)日：2024-02-15

申请号：US18266782

申请日：2021-12-08

Applicant: Rambus Inc.

Inventor： Srinivas Satish Babu Bamdhamravuri ,  Panduka Wijetunga

IPC: G11C29/50 ,  G11C29/56

CPC classification number: G11C29/50012 ,  G11C29/56012 ,  G11C29/56004 ,  G11C2029/5602

Abstract: Technologies for signal skew correction in integrated circuit memory devices are described. An integrated circuit memory device includes a first interface to receive command/address (CA) signals and a clock signal, a data interface, and a mode register. During a CA bus loopback mode, the first interface receives a pattern of CA signals and the clock signal and the data interface outputs the pattern of CA signals. During the CA bus loopback mode, the mode register can be programmed with a value representative of a timing offset between the clock signal and a sampling point for the first interface.

公开(公告)号：US11829640B2

公开(公告)日：2023-11-28

申请号：US17451754

申请日：2021-10-21

Applicant: Rambus Inc.

Inventor： Srinivas Satish Babu Bamdhamravuri

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.

公开(公告)号：US20220129201A1

公开(公告)日：2022-04-28

申请号：US17451754

申请日：2021-10-21

Applicant: Rambus Inc.

Inventor： Srinivas Satish Babu Bamdhamravuri

IPC: G06F3/06

Abstract: A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.

公开(公告)号：US20240231699A9

公开(公告)日：2024-07-11

申请号：US18497888

申请日：2023-10-30

Applicant: Rambus Inc.

Inventor： Srinivas Satish Babu Bamdhamravuri

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.

公开(公告)号：US20240134574A1

公开(公告)日：2024-04-25

申请号：US18497888

申请日：2023-10-29

Applicant: Rambus Inc.

Inventor： Srinivas Satish Babu Bamdhamravuri

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.

公开(公告)号：US11782476B2

公开(公告)日：2023-10-10

申请号：US17529515

申请日：2021-11-18

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Marcial Chua ,  Srinivas Satish Babu Bamdhamravuri ,  Abhishek Desai ,  Philip Lu ,  Cosmin Iorga

IPC: G06F1/10

CPC classification number: G06F1/10

Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

公开(公告)号：US20220179444A1

公开(公告)日：2022-06-09

申请号：US17529515

申请日：2021-11-18

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Marcial Chua ,  Srinivas Satish Babu Bamdhamravuri ,  Abhishek Desai ,  Philip Lu ,  Cosmin Iorga

IPC: G06F1/10

Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.