公开(公告)号：US11900985B1

公开(公告)日：2024-02-13

申请号：US17405527

申请日：2021-08-18

申请人： Rambus Inc.

发明人： Panduka Wijetunga ,  Abhishek Desai

IPC分类号： G11C11/4076 ,  G06F1/06 ,  H03K3/017

CPC分类号： G11C11/4076 ,  G06F1/06 ,  H03K3/017

摘要： A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.

公开(公告)号：US11782476B2

公开(公告)日：2023-10-10

申请号：US17529515

申请日：2021-11-18

申请人： Rambus Inc.

发明人： Panduka Wijetunga ,  Marcial Chua ,  Srinivas Satish Babu Bamdhamravuri ,  Abhishek Desai ,  Philip Lu ,  Cosmin Iorga

IPC分类号： G06F1/10

CPC分类号： G06F1/10

摘要： A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

公开(公告)号：US20220179444A1

公开(公告)日：2022-06-09

申请号：US17529515

申请日：2021-11-18

申请人： Rambus Inc.

发明人： Panduka Wijetunga ,  Marcial Chua ,  Srinivas Satish Babu Bamdhamravuri ,  Abhishek Desai ,  Philip Lu ,  Cosmin Iorga

IPC分类号： G06F1/10

摘要： A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.