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    RECEIVER TRAINING OF REFERENCE VOLTAGE AND EQUALIZER COEFFICIENTS
    2.
    发明申请
    RECEIVER TRAINING OF REFERENCE VOLTAGE AND EQUALIZER COEFFICIENTS 有权

    公开(公告)号：US20210090675A1

    公开(公告)日：2021-03-25

    申请号：US17026133

    申请日：2020-09-18

    Applicant: Rambus Inc.

    Inventor： Ashwin S. M. ,  Anirudha Shelke ,  Navin Kumar Mishra ,  Phalguni Bala ,  Younus Syed ,  Kiran Baby ,  Sudhir Kumar Katla Shetty

    IPC: G11C29/36 ,  G11C29/50 ,  G11C7/22

    Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be245 adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.

    Strobe gating adaption and training in a memory controller
    3.
    发明授权
    Strobe gating adaption and training in a memory controller 有权
    在内存控制器中选通门控适应和训练

    公开(公告)号：US09514420B2

    公开(公告)日：2016-12-06

    申请号：US14824080

    申请日：2015-08-12

    Applicant: Rambus Inc.

    Inventor： Soumya Bose ,  Navin Kumar Mishra ,  Abhilash Puzhankara ,  Mahabaleshwara Mahabaleshwara ,  Karthikeyan Swamiappan

    IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06 ,  G11C7/08 ,  G06N99/00 ,  G06F13/16 ,  G11C11/4096

    CPC classification number: G06N99/005 ,  G06F13/1668 ,  G11C7/06 ,  G11C7/067 ,  G11C7/1078 ,  G11C11/4096 ,  G11C2207/2254

    Abstract: A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

    Abstract translation: 存储器控制器包括差分接收器电路，用于接收差分数据选通信号对，并且基于差分数据选通信号对产生第一数据选通信号。 差分数据选通信号对包括第一信号和第二信号。 存储器控制器还包括用于接收差分数据选通信号对的第一信号的单端接收器电路，并且基于差分数据选通信号对的第一信号产生第二数据选通信号。 存储器控制器还包括用于产生用于选通第一数据选通信号的门控信号的电路，该电路基于第二数据选通信号产生门控信号。

    DRIVER CIRCUIT
    4.
    发明申请
    DRIVER CIRCUIT 有权
    驱动电路

    公开(公告)号：US20150103607A1

    公开(公告)日：2015-04-16

    申请号：US14574126

    申请日：2014-12-17

    Applicant: Rambus Inc.

    Inventor： Manish Jain ,  Navin Kumar Mishra

    IPC: G11C11/4094 ,  G11C11/4076

    CPC classification number: G11C11/4094 ,  G06F13/4072 ,  G11C7/00 ,  G11C11/4076 ,  H03L7/00

    Abstract: A method of operation in a memory controller includes operating pull-up and pull-down drivers driven by separate pre-drivers between different voltage rails. Data signals driving the pull-up driver and the pull-down driver are synchronized, and the pull-up driver and the pull-down driver are coupled together to produce an output signal having a voltage swing based on both the pull-up driver and the pull-down driver.

    Abstract translation: 存储器控制器中的操作方法包括由不同电压轨之间的分离的预驱动器驱动的操作上拉和下拉驱动器。 驱动上拉驱动器和下拉驱动器的数据信号被同步，并且上拉驱动器和下拉驱动器耦合在一起以产生具有基于上拉驱动器和 下拉驱动程序。

    High-resolution digitally controlled delay line
    5.
    发明授权
    High-resolution digitally controlled delay line 有权

    公开(公告)号：US11183995B1

    公开(公告)日：2021-11-23

    申请号：US15945523

    申请日：2018-04-04

    Applicant: Rambus Inc.

    Inventor： Anirudha Shelke ,  Navin Kumar Mishra

    IPC: H03K5/131 ,  H03K5/133 ,  H03K5/135 ,  H03K5/00 ,  G11C7/22

    Abstract: In a delay control circuit having a plurality of series-coupled delay stages, an input signal is routed through one of the series-coupled delay stages via a first delay element if a first delay control value is in a first state, the first delay element imposing a first signal propagation delay according to a first bias signal. If the delay control value is in a second state, the input signal is routed through the one of the series-coupled delay stages via a second delay element instead of the first delay element, the second delay element imposing a second signal propagation delay according to a second bias signal. The first and second bias signals are calibrated such that the second signal propagation delay exceeds the first propagation delay by a predetermined time interval that is substantially briefer than the first signal propagation delay.

    Driver circuit
    7.
    发明授权
    Driver circuit 有权
    驱动电路

    公开(公告)号：US09449676B2

    公开(公告)日：2016-09-20

    申请号：US14574126

    申请日：2014-12-17

    Applicant: Rambus Inc.

    Inventor： Manish Jain ,  Navin Kumar Mishra

    IPC: G11C7/00 ,  G11C11/4094 ,  H03L7/00 ,  G11C11/4076 ,  G06F13/40

    CPC classification number: G11C11/4094 ,  G06F13/4072 ,  G11C7/00 ,  G11C11/4076 ,  H03L7/00

    Abstract: A method of operation in a memory controller includes operating pull-up and pull-down drivers driven by separate pre-drivers between different voltage rails. Data signals driving the pull-up driver and the pull-down driver are synchronized, and the pull-up driver and the pull-down driver are coupled together to produce an output signal having a voltage swing based on both the pull-up driver and the pull-down driver.

    Abstract translation: 存储器控制器中的操作方法包括由不同电压轨之间的分离的预驱动器驱动的操作上拉和下拉驱动器。 驱动上拉驱动器和下拉驱动器的数据信号被同步，并且上拉驱动器和下拉驱动器耦合在一起以产生具有基于上拉驱动器和 下拉驱动程序。

    Receiver training of reference voltage and equalizer coefficients
    9.
    发明授权
    Receiver training of reference voltage and equalizer coefficients 有权

    公开(公告)号：US11133081B2

    公开(公告)日：2021-09-28

    申请号：US17026133

    申请日：2020-09-18

    Applicant: Rambus Inc.

    Inventor： Ashwin S. M. ,  Anirudha Shelke ,  Navin Kumar Mishra ,  Phalguni Bala ,  Younus Syed ,  Kiran Baby ,  Sudhir Kumar Katla Shetty

    IPC: G11C7/10 ,  G11C29/36 ,  G11C7/22 ,  G11C29/50

    Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.

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