公开(公告)号：US09836412B2

公开(公告)日：2017-12-05

申请号：US14707166

申请日：2015-05-08

Applicant: Rambus Inc.

Inventor： Ray McConnell

IPC: G06F12/10 ,  G06F12/109 ,  G06F11/30 ,  G06F9/46 ,  G06F15/173 ,  G06F15/80

CPC classification number: G06F13/1657 ,  G06F9/46 ,  G06F11/3017 ,  G06F12/109 ,  G06F15/17337 ,  G06F15/8015 ,  G06F2212/657

Abstract: A plurality of processing elements (PEs) include memory local to at least one of the processing elements in a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid to connect the PEs and their local memories to a common controller. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. The packet-switched network supports multiple concurrent transfers between PEs and memory. Memory accesses include block and/or broadcast read and write operations, in which data can be replicated within the nodes and, according to the operation, written into the shared memory or into the local PE memory.

公开(公告)号：US20160283241A1

公开(公告)日：2016-09-29

申请号：US15073573

申请日：2016-03-17

Applicant: Rambus Inc.

Inventor： Dave Stuttard ,  Dave Williams ,  Eamon O'Dea ,  Gordon Faulds ,  John Rhoades ,  Ken Cameron ,  Phil Atkin ,  Paul Winser ,  Russell David ,  Ray McConnell ,  Tim Day ,  Trey Greer

IPC: G06F9/38 ,  G06F15/80 ,  G06F9/30

CPC classification number: G06F9/38 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/5088 ,  G06F15/8007

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.

Abstract translation: 数据处理装置包括以单指令多数据阵列排列的多个处理元件。 该装置包括指令控制器，其可操作以从多个指令流接收指令，并将指令从这些指令流传送到阵列中的处理元件，使得数据处理装置可操作以基本上处理多个处理线程 彼此平行。 提供了数据传输控制器，其可操作以控制与处理元件相关联的内部存储器单元与阵列外部的存储器之间的数据传输。