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公开(公告)号：US20210271301A1
公开(公告)日：2021-09-02
申请号：US17141102
申请日：2021-01-04
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
Abstract: A circuit interface includes one or more processors that generate opcodes, a plurality of interface control circuits, each including a respective processing element responsive to the opcodes generated by one or more processors. Each interface control circuit corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more destinations external to the circuit.
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2.发明申请Generating Interface Adjustment Signals in a Device-To-Device Interconnection System 有权在设备到设备间互连系统中生成接口调整信号公开(公告)号：US20130346663A1
公开(公告)日：2013-12-26
申请号：US13747419
申请日：2013-01-22
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
IPC: G06F13/38
CPC classification number: G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G06F2212/7201 , G11C7/1072 , H03K19/1776 , H04L7/02
Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
Abstract translation: 描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。 处理器可以通过总线的一个或多个总线接口耦合到一个或多个对应的接口定时和/或电压比较电路以及对应的接口定时和/或电压调节电路。
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3.发明授权Generating interface adjustment signals in a device-to-device interconnection system 有权在设备到设备互连系统中生成接口调整信号公开(公告)号：US09117031B2
公开(公告)日：2015-08-25
申请号：US14329791
申请日：2014-07-11
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
CPC classification number: G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G06F2212/7201 , G11C7/1072 , H03K19/1776 , H04L7/02
Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
Abstract translation: 描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。 处理器可以通过总线的一个或多个总线接口耦合到一个或多个对应的接口定时和/或电压比较电路以及对应的接口定时和/或电压调节电路。
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4.发明申请Generating Interface Adjustment Signals in a Device-To-Device Interconnection System 有权在设备到设备间互连系统中生成接口调整信号公开(公告)号：US20140325252A1
公开(公告)日：2014-10-30
申请号：US14329791
申请日：2014-07-11
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
IPC: G06F1/10
CPC classification number: G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G06F2212/7201 , G11C7/1072 , H03K19/1776 , H04L7/02
Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
Abstract translation: 描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。 处理器可以通过总线的一个或多个总线接口耦合到一个或多个对应的接口定时和/或电压比较电路以及对应的接口定时和/或电压调节电路。
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5.发明授权Generating interface adjustment signals in a device-to-device interconnection system 有权在设备到设备互连系统中生成接口调整信号公开(公告)号：US08782578B2
公开(公告)日：2014-07-15
申请号：US13747419
申请日：2013-01-22
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
IPC: G06F17/50
CPC classification number: G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G06F2212/7201 , G11C7/1072 , H03K19/1776 , H04L7/02
Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
Abstract translation: 描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。 处理器可以通过总线的一个或多个总线接口耦合到一个或多个对应的接口定时和/或电压比较电路以及对应的接口定时和/或电压调节电路。
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Patent Agency Ranking
公开(公告)号：US11681342B2
公开(公告)日：2023-06-20
申请号：US17141102
申请日：2021-01-04
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
IPC: G06F12/00 , G06F1/26 , G06F13/40 , H04L7/02 , G06F1/10 , G06F13/38 , G06F12/02 , G11C7/10 , H03K19/1776
CPC classification number: G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G11C7/1072 , H03K19/1776 , H04L7/02 , G06F2212/7201
Abstract: A circuit interface includes one or more processors that generate opcodes, a plurality of interface control circuits, each including a respective processing element responsive to the opcodes generated by one or more processors. Each interface control circuit corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more destinations external to the circuit.
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公开(公告)号：US09965008B2
公开(公告)日：2018-05-08
申请号：US14835568
申请日：2015-08-25
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
CPC classification number: G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G06F2212/7201 , G11C7/1072 , H03K19/1776 , H04L7/02
Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
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公开(公告)号：US10884465B2
公开(公告)日：2021-01-05
申请号：US15972025
申请日：2018-05-04
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
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公开(公告)号：US20180348832A1
公开(公告)日：2018-12-06
申请号：US15972025
申请日：2018-05-04
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
CPC classification number: G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G06F2212/7201 , G11C7/1072 , H03K19/1776 , H04L7/02
Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
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10.发明申请Memory Controller with Processor for Generating Interface Adjustment Signals 有权具有处理器的存储器控制器，用于生成接口调整信号公开(公告)号：US20150362967A1
公开(公告)日：2015-12-17
申请号：US14835568
申请日：2015-08-25
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
IPC: G06F1/26 , G06F12/02 , G11C7/10 , H03K19/177
CPC classification number: G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G06F2212/7201 , G11C7/1072 , H03K19/1776 , H04L7/02
Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
Abstract translation: 描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。 处理器可以通过总线的一个或多个总线接口耦合到一个或多个对应的接口定时和/或电压比较电路以及对应的接口定时和/或电压调节电路。
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