Methods and circuits for reducing clock jitter
    1.
    发明授权
    Methods and circuits for reducing clock jitter 有权
    减少时钟抖动的方法和电路

    公开(公告)号:US09397823B2

    公开(公告)日:2016-07-19

    申请号:US14518061

    申请日:2014-10-20

    Applicant: Rambus Inc.

    CPC classification number: H04L7/02 H03K5/1252 H03L7/00

    Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

    Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化,包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度,否则需要快速打开系统。

    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER
    2.
    发明申请
    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER 有权
    减少时钟抖动的方法和电路

    公开(公告)号:US20150036775A1

    公开(公告)日:2015-02-05

    申请号:US14518061

    申请日:2014-10-20

    Applicant: Rambus Inc.

    CPC classification number: H04L7/02 H03K5/1252 H03L7/00

    Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

    Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化,包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度,否则需要快速打开系统。

    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER
    3.
    发明申请
    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER 有权
    减少时钟抖动的方法和电路

    公开(公告)号:US20140152357A1

    公开(公告)日:2014-06-05

    申请号:US13878351

    申请日:2011-10-03

    Applicant: RAMBUS INC.

    CPC classification number: H04L7/02 H03K5/1252 H03L7/00

    Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

    Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化,包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度,否则需要快速打开系统。

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