公开(公告)号：US20130188436A1

公开(公告)日：2013-07-25

申请号：US13726433

申请日：2012-12-24

Applicant: Rambus Inc.

Inventor： Vidhya Thyagarajan ,  Sudhir Shetty

IPC: G11C5/14

CPC classification number: G11C5/148

Abstract: Methods and apparatuses that relate to an integrated circuit (IC) with adaptive power state management are described. The IC can be coupled with, and can control the operation of, a memory device. The IC and the memory device can be operated in multiple operational states, wherein each operational state may represent a tradeoff point between performance and power consumption. The IC may be capable of: (1) changing the operational state of the IC and/or the operational state of the memory device based on the occurrence of one or more conditions, and/or (2) changing the one or more conditions based on measuring one or more performance values associated with the IC and/or the memory device.

Abstract translation: 描述与具有自适应功率状态管理的集成电路（IC）相关的方法和装置。 IC可以与存储器件耦合并且可以控制存储器件的操作。 IC和存储器件可以在多个操作状态下操作，其中每个操作状态可以表示性能和功耗之间的权衡点。 IC可能能够：（1）基于一个或多个条件的发生来改变IC的操作状态和/或存储设备的操作状态，和/或（2）改变一个或多个基于条件的 测量与IC和/或存储器件相关联的一个或多个性能值。

公开(公告)号：US09117508B2

公开(公告)日：2015-08-25

申请号：US13726433

申请日：2012-12-24

Applicant: Rambus Inc.

Inventor： Vidhya Thyagarajan ,  Sudhir Shetty

IPC: G11C5/14

CPC classification number: G11C5/148

Abstract: Methods and apparatuses that relate to an integrated circuit (IC) with adaptive power state management are described. The IC can be coupled with, and can control the operation of, a memory device. The IC and the memory device can be operated in multiple operational states, wherein each operational state may represent a tradeoff point between performance and power consumption. The IC may be capable of: (1) changing the operational state of the IC and/or the operational state of the memory device based on the occurrence of one or more conditions, and/or (2) changing the one or more conditions based on measuring one or more performance values associated with the IC and/or the memory device.

Abstract translation: 描述与具有自适应功率状态管理的集成电路（IC）相关的方法和装置。 IC可以与存储器件耦合并且可以控制存储器件的操作。 IC和存储器件可以在多个操作状态下操作，其中每个操作状态可以表示性能和功耗之间的权衡点。 IC可能能够：（1）基于一个或多个条件的发生来改变IC的操作状态和/或存储设备的操作状态，和/或（2）改变一个或多个基于条件的 测量与IC和/或存储器件相关联的一个或多个性能值。

公开(公告)号：US08990490B2

公开(公告)日：2015-03-24

申请号：US13686643

申请日：2012-11-27

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Vidhya Thyagarajan ,  Prasanna Kole ,  Gidda Reddy Gangula

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/0646 ,  G06F13/16 ,  G06F13/1642 ,  Y02D10/13 ,  Y02D10/14

Abstract: Memory controller concepts are disclosed in which hardware resources of a memory controller can be re-used or re-configured to accommodate various different memory configurations. The memory configuration may be stored in mode register bits (228), settable by a host or operating system. By re-configuring or reallocating certain resources of a memory controller, for example command logic blocks (A, B, C, D in FIG. 1A), a single controller design can be used to interface efficiently with a variety of different memory components. Command logic blocks that support N×M memory ranks, for example, can be reconfigured to support N ranks and M threads for multi-threaded memories (FIG. 1A). Data buffer (232, 254) depth can be extended by reconfiguring the buffers responsive to the mode register bits (228). Request buffers can be shared across command logic blocks, for example to increase the request buffer depth (FIG. 3A). Unused circuits can be powered down to save power consumption (FIG. 4A).

Abstract translation: 公开了存储器控制器概念，其中可以重新使用或重新配置存储器控制器的硬件资源以适应各种不同的存储器配置。 存储器配置可以存储在由主机或操作系统设置的模式寄存器位（228）中。 通过重新配置或重新分配存储器控制器的某些资源，例如命令逻辑块（图1A中的A，B，C，D），可以使用单个控制器设计来有效地与各种不同的存储器组件进行接口。 例如，支持N×M内存等级的命令逻辑块可被重新配置为支持用于多线程存储器的N个队列和M个线程（图1A）。 可以通过根据模式寄存器位重新配置缓冲区来扩展数据缓冲区（232,254）的深度（228）。 请求缓冲区可以在命令逻辑块之间共享，例如增加请求缓冲区深度（图3A）。 未使用的电路可以掉电以节省功耗（图4A）。

公开(公告)号：US20140052906A1

公开(公告)日：2014-02-20

申请号：US13959500

申请日：2013-08-05

Applicant: Rambus Inc.

Inventor： Vidhya Thyagarajan ,  Prasanna Kole ,  Dinesh Malviya

IPC: G11C7/10 ,  G06F12/00

CPC classification number: G11C7/1072 ,  G06F12/00 ,  G06F13/16 ,  G06F13/161 ,  G06F13/1684

Abstract: A multi-channel memory controller (110, 600) may be dynamically re-architected to schedule low and high-latency memory access requests differently (FIG. 12) in order to make more efficient use of memory resources and improve overall performance. Data may be duplicated or “cloned” in a clone area (612) of one or more channels of a multi-channel or module threaded memory (610), the clone area being reserved by the memory controller. Cloning information is stored in a clone mapping table 620, preferably reflecting memory channel locations, including clone locations, per memory address range. An operating system may request a selected number of channels for cloning, see (622), based on application latency requirements or sensitivity, by storing the request in the clone mapping table. Coarse granularity access requests also may be dynamically scheduled across one or more first-available channels of the multi-channel or module threaded memory (1504) in a modified controller (1500).

Abstract translation: 可以动态重新设计多通道存储器控制器（110,600）以不同地调度低和高延迟的存储器访问请求（图12），以便更有效地使用存储器资源并提高整体性能。 可以将数据复制或“克隆”在多通道或模块螺纹存储器（610）的一个或多个通道的克隆区域（612）中，克隆区域由存储器控制器保留。 克隆信息存储在克隆映射表620中，优选地反映每个存储器地址范围的包括克隆位置的存储器通道位置。 通过将请求存储在克隆映射表中，操作系统可以基于应用等待时间要求或灵敏度来请求选择数量的用于克隆的信道，参见（622）。 粗粒度访问请求也可以在修改的控制器（1500）中的多信道或模块螺纹存储器（1504）的一个或多个第一可用信道上动态地调度。

公开(公告)号：US20130138911A1

公开(公告)日：2013-05-30

申请号：US13686643

申请日：2012-11-27

Applicant: Rambus Inc.

Inventor： Liji GOPALAKRISHNAN ,  Vidhya Thyagarajan ,  Prasanna Kole ,  Gidda Reddy Gangula

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G06F13/16 ,  G06F13/1642 ,  Y02D10/13 ,  Y02D10/14

Abstract: Memory controller concepts are disclosed in which hardware resources of a memory controller can be re-used or re-configured to accommodate various different memory configurations. The memory configuration may be stored in mode register bits (228), settable by a host or operating system. By re-configuring or reallocating certain resources of a memory controller, for example command logic blocks (A,B,C,D in FIG. 1A), a single controller design can be used to interface efficiently with a variety of different memory components. Command logic blocks that support N×M memory ranks, for example, can be reconfigured to support N ranks and M threads for multi-threaded memories (FIG. 1A). Data buffer (232, 254) depth can be extended by reconfiguring the buffers responsive to the mode register bits (228). Request buffers can be shared across command logic blocks, for example to increase the request buffer depth (FIG. 3A). Unused circuits can be powered down to save power consumption (FIG. 4A).

Abstract translation: 公开了存储器控制器概念，其中可以重新使用或重新配置存储器控制器的硬件资源以适应各种不同的存储器配置。 存储器配置可以存储在由主机或操作系统设置的模式寄存器位（228）中。 通过重新配置或重新分配存储器控制器的某些资源，例如命令逻辑块（图1A中的A，B，C，D），可以使用单个控制器设计来有效地与各种不同的存储器组件进行接口。 例如，支持N×M内存等级的命令逻辑块可被重新配置为支持用于多线程存储器的N个队列和M个线程（图1A）。 可以通过根据模式寄存器位（228）重新配置缓冲区来扩展数据缓冲区（232,254）的深度。 请求缓冲区可以跨命令逻辑块共享，例如增加请求缓冲区深度（图3A）。 未使用的电路可以掉电以节省功耗（图4A）。