公开(公告)号：US11677391B1

公开(公告)日：2023-06-13

申请号：US17585297

申请日：2022-01-26

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  Andrew M. Fuller ,  William F. Stonecypher

IPC: H03K5/01 ,  G06F1/12 ,  H03K5/00

CPC classification number: H03K5/01 ,  G06F1/12 ,  H03K2005/00019

Abstract: A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.

公开(公告)号：US09892771B2

公开(公告)日：2018-02-13

申请号：US15126868

申请日：2015-03-24

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  William F. Stonecypher

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/10

Abstract: In a memory controller having a controller core and a physical signaling interface, the controller core outputs a request for read data to the physical signaling interface specifying one of at least two memory components from which the read data is to be retrieved. In response to the request for read data, the physical signaling interface outputs a memory read request to the specified memory component, receives the read data from the specified memory component, and transfers the read data to the controller core at either a first time or a second time according to whether the specified memory component is a first memory component or second memory component of the at least two memory components.

公开(公告)号：US20170092343A1

公开(公告)日：2017-03-30

申请号：US15126868

申请日：2015-03-24

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  William F. Stonecypher

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/10

Abstract: In a memory controller having a controller core and a physical signaling interface, the controller core outputs a request for read data to the physical signaling interface specifying one of at least two memory components from which the read data is to be retrieved. In response to the request for read data, the physical signaling interface outputs a memory read request to the specified memory component, receives the read data from the specified memory component, and transfers the read data to the controller core at either a first time or a second time according to whether the specified memory component is a first memory component or second memory component of the at least two memory components.

公开(公告)号：US09368172B2

公开(公告)日：2016-06-14

申请号：US14572674

申请日：2014-12-16

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  Barry W. Daly ,  William F. Stonecypher

IPC: G11C7/00 ,  G11C7/22

CPC classification number: G11C7/22 ,  G06F13/1689

Abstract: A memory controller that extends the window when reading data from the memory device to compensate for fluctuations in a read strobe delay. The memory controller includes a communication port that receives a timing reference signal for reading data from a memory device. A control circuit generates a gating signal indicative of a read window. A gating adjustment circuit generates an adjusted gating signal indicative of an adjusted read window based on the gating signal and the timing reference signal. A gating circuit generates a first gated timing reference signal for reading data by gating a delayed version of the timing reference signal with the adjusted gating signal.

Abstract translation: 存储器控制器，当从存储器件读取数据以补偿读取选通延迟的波动时，扩展窗口。 存储器控制器包括接收用于从存储器件读取数据的定时参考信号的通信端口。 控制电路产生指示读窗口的门控信号。 门控调整电路基于门控信号和定时参考信号产生指示经调整的读窗口的调整门控信号。 选通电路产生用于通过利用调整的门控信号门控定时参考信号的延迟版本来读取数据的第一选通定时参考信号。

公开(公告)号：US20150221354A1

公开(公告)日：2015-08-06

申请号：US14572674

申请日：2014-12-16

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  Barry W. Daly ,  William F. Stonecypher

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G06F13/1689

Abstract: A memory controller that extends the window when reading data from the memory device to compensate for fluctuations in a read strobe delay. The memory controller includes a communication port that receives a timing reference signal for reading data from a memory device. A control circuit generates a gating signal indicative of a read window. A gating adjustment circuit generates an adjusted gating signal indicative of an adjusted read window based on the gating signal and the timing reference signal. A gating circuit generates a first gated timing reference signal for reading data by gating a delayed version of the timing reference signal with the adjusted gating signal.

Abstract translation: 存储器控制器，当从存储器件读取数据以补偿读取选通延迟的波动时，扩展窗口。 存储器控制器包括接收用于从存储器件读取数据的定时参考信号的通信端口。 控制电路产生指示读窗口的门控信号。 门控调整电路基于门控信号和定时参考信号产生指示经调整的读窗口的调整门控信号。 选通电路产生用于通过利用调整的门控信号门控定时参考信号的延迟版本来读取数据的第一选通定时参考信号。