公开(公告)号：US20240428835A1

公开(公告)日：2024-12-26

申请号：US18767988

申请日：2024-07-10

Applicant: Rambus Inc.

Inventor： Andrew M. Fuller ,  Robert E. Palmer ,  Thomas J. Giovannini ,  Michael D. Bucher ,  Thoai Thai Le

IPC: G11C7/22 ,  G11C7/10

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

公开(公告)号：US20240168873A1

公开(公告)日：2024-05-23

申请号：US18162824

申请日：2021-08-06

Applicant: Rambus Inc.

Inventor： Andrew M. Fuller ,  Barry William Daly ,  Thomas J. Giovannini ,  Lei Luo ,  Masum Hossain

IPC: G06F12/02 ,  G11C11/408

CPC classification number: G06F12/0223 ,  G11C11/4082

Abstract: Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing-reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.

公开(公告)号：US20200012332A1

公开(公告)日：2020-01-09

申请号：US16418259

申请日：2019-05-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/3237 ,  G06F3/06 ,  G06F1/324 ,  G06F1/3225 ,  G06F1/12 ,  G11C7/22 ,  G06F13/16 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/04

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US09753521B2

公开(公告)日：2017-09-05

申请号：US14951150

申请日：2015-11-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F3/06 ,  G06F9/38 ,  G06F12/0855 ,  G06F13/36

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.

公开(公告)号：US20150074437A1

公开(公告)日：2015-03-12

申请号：US14546687

申请日：2014-11-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/12 ,  G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Abstract translation: 集成电路存储器控制器向存储器件输出处于第一状态的第一信号，以使存储器件内的同步数据发送和接收电路能够操作。 存储器控制器内的事务队列存储要被服务的存储器读和写请求，分别要求存储器件内的同步数据发送和接收电路的操作。 存储器控制器内的电源控制电路确定事务队列已经达到预定状态，并且作为响应，在第二状态下将第一信号输出到存储器件，以禁止存储器件内的同步数据发送和接收电路的操作。

公开(公告)号：US12062413B1

公开(公告)日：2024-08-13

申请号：US18234288

申请日：2023-08-15

Applicant: Rambus Inc.

Inventor： Andrew M. Fuller ,  Robert E. Palmer ,  Thomas J. Giovannini ,  Michael D. Bucher ,  Thoai Thai Le

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

公开(公告)号：US20230244293A1

公开(公告)日：2023-08-03

申请号：US18092004

申请日：2022-12-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/3237 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/06

CPC classification number: G06F1/3237 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/1689 ,  G11C7/22 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US11677391B1

公开(公告)日：2023-06-13

申请号：US17585297

申请日：2022-01-26

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  Andrew M. Fuller ,  William F. Stonecypher

IPC: H03K5/01 ,  G06F1/12 ,  H03K5/00

CPC classification number: H03K5/01 ,  G06F1/12 ,  H03K2005/00019

Abstract: A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.

公开(公告)号：US20180067538A1

公开(公告)日：2018-03-08

申请号：US15682257

申请日：2017-08-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/32 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/22 ,  G06F1/12 ,  G11C7/04 ,  G06F13/16 ,  G06F9/38 ,  G06F13/36

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US20150227188A1

公开(公告)日：2015-08-13

申请号：US14694046

申请日：2015-04-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract translation: 存储器系统的存储器控​​制器组件将存储器访问请求存储在事务队列中，直到被服务，使得随着时间的推移，事务队列在被占用和空状态之间交替。 响应于检测到事务队列已经保持在空状态达预定时间，存储器控制器将存储器系统转换到低功率模式。 在向低功率模式的转变中，存储器控制器禁用在一个或多个附加存储器件的同步通信电路内对时间数据信号操作所需的一个或多个定时信号的振荡，并且还禁用同步通信中的一个或多个功耗电路 一个或多个存储器件的电路。