公开(公告)号：US20190043960A1

公开(公告)日：2019-02-07

申请号：US16022540

申请日：2018-06-28

申请人： Randy Koval ,  Srikant Jayanti ,  Hiroyuki Sanda ,  Meng-Wei Kuo ,  Srivardhan Gowda ,  Krishna Parat

发明人： Randy Koval ,  Srikant Jayanti ,  Hiroyuki Sanda ,  Meng-Wei Kuo ,  Srivardhan Gowda ,  Krishna Parat

IPC分类号： H01L29/423 ,  H01L27/11556 ,  H01L27/11521 ,  H01L29/06 ,  H01L29/10 ,  H01L29/04 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

摘要： A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.