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1.发明授权公开(公告)号：US07039760B2
公开(公告)日：2006-05-02
申请号：US10425443
申请日：2003-04-28
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/127
摘要： A method and apparatus for managing cache lines in a data processing system. A special purpose register is employed in which this register may be manipulated by user code and operating system code to set preferences, such as a level 2 cache management policy preference for an application thread. These preferences may be dynamically set and an arbitration mechanism is employed to best satisfy preferences of multiple threads with a single aggregate preference. Members are represented using a least recently used tree. The least recent used tree has a set of nodes forming a path to member cache lines in a hierarchical structure. A state of a selected node is selectively biased within the set of nodes in the least recently used tree. At least one node on a level below the selected node is eliminated from being selected in managing the cache lines. In this manner, members can be biased against or for selection as victims when replacing cache lines in a cache memory.
摘要翻译： 一种用于在数据处理系统中管理高速缓存行的方法和装置。 使用专用寄存器，其中该寄存器可以由用户代码和操作系统代码来操作以设置优先级，诸如针对应用程序线程的2级缓存管理策略偏好。 这些偏好可以被动态设置，并且使用仲裁机制来最好地满足具有单个聚合偏好的多个线程的偏好。 会员使用最近最少使用的树来表示。 最近使用的树具有一组以层次结构形成到成员高速缓存行的路径的节点。 所选节点的状态在最近最少使用的树中的节点集合内被有选择地偏置。 在选择的节点以下的级别上的至少一个节点在管理高速缓存行时被排除。 以这种方式，当替换高速缓冲存储器中的高速缓存行时，成员可以偏向于或被选择为受害者。
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公开(公告)号：US07530063B2
公开(公告)日：2009-05-05
申请号：US10855729
申请日：2004-05-27
申请人： Roch Georges Archambault , Robert James Blainey , Yaoqing Gao , John David McCalpin , Francis Patrick O'Connell , Pascal Vezolle , Steven Wayne White
发明人： Roch Georges Archambault , Robert James Blainey , Yaoqing Gao , John David McCalpin , Francis Patrick O'Connell , Pascal Vezolle , Steven Wayne White
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a modification factor for the instructions based on a number of separate equivalent sections forming a cache in a processor which is processing the instructions; and modifying the instructions to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.
摘要翻译： 提供了修改形成循环的指令的方法和系统。 修改形成循环的指令的方法包括修改形成循环的指令，包括：确定指令的静态和动态特性; 基于在正在处理所述指令的处理器中形成高速缓存的单独的等效部分的数量来选择所述指令的修改因子; 以及当指令满足基于静态和动态特性的修改标准时，修改指令以根据修改因子和静态和动态特性来交织循环中的指令。
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公开(公告)号：US07194587B2
公开(公告)日：2007-03-20
申请号：US10422677
申请日：2003-04-24
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0804 , G06F12/0808 , G06F12/0837 , G06F12/0891
摘要： A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending references to a cache block corresponding to the determined effective address to commit to the cache subsystem. If the referenced cache line is modified in the local cache (the cache subsystem corresponding to the processor executing the instruction), it is then written back to main memory. If the referenced block is valid in the local cache it is invalidated, but only in the local cache. If the referenced block is not valid in the local cache, there is no invalidation. Remote processors receiving a local cache block flush instruction from another processor via the system ignore the instruction.
摘要翻译： 微处理器和相关编译器支持本地缓存块刷新指令，其中处理器的执行单元确定有效地址。 处理器强制所有未决引用对应于所确定的有效地址的缓存块以提交到缓存子系统。 如果引用的高速缓存行在本地缓存（与执行指令的处理器相对应的缓存子系统）中被修改，则将其写回主存储器。 如果引用的块在本地缓存中有效，则它将被无效，但仅在本地缓存中。 如果引用的块在本地缓存中无效，则不会产生无效。 通过系统从另一个处理器接收本地缓存块刷新指令的远程处理器忽略该指令。
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