公开(公告)号：US07530063B2

公开(公告)日：2009-05-05

申请号：US10855729

申请日：2004-05-27

申请人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoqing Gao ,  John David McCalpin ,  Francis Patrick O'Connell ,  Pascal Vezolle ,  Steven Wayne White

发明人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoqing Gao ,  John David McCalpin ,  Francis Patrick O'Connell ,  Pascal Vezolle ,  Steven Wayne White

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a modification factor for the instructions based on a number of separate equivalent sections forming a cache in a processor which is processing the instructions; and modifying the instructions to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.

摘要翻译： 提供了修改形成循环的指令的方法和系统。 修改形成循环的指令的方法包括修改形成循环的指令，包括：确定指令的静态和动态特性; 基于在正在处理所述指令的处理器中形成高速缓存的单独的等效部分的数量来选择所述指令的修改因子; 以及当指令满足基于静态和动态特性的修改标准时，修改指令以根据修改因子和静态和动态特性来交织循环中的指令。

公开(公告)号：US07168070B2

公开(公告)日：2007-01-23

申请号：US10853304

申请日：2004-05-25

申请人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoging Gao ,  Randall Ray Heisch ,  Steven Wayne White

发明人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoging Gao ,  Randall Ray Heisch ,  Steven Wayne White

IPC分类号： G06F9/45 ,  G06F13/00

CPC分类号： G06F12/0833 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383

摘要： A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.

摘要翻译： 与底层硬件负载流预取支持协作，通过数据缓存块零（DCBZ）指令减少或避免存储错误的方法和系统，以帮助增加有效的聚合带宽。 该方法基于依赖和重用分析在循环中识别和分类唯一流，并执行循环转换，例如节点分割，循环分布或流展开以获得适当数量的流。 静态预测和运行时间轮廓信息用于指导循环和流选择。 编译时循环成本分析和运行时检查代码和版本控制用于确定数据高速缓存行归零的每个引用之前的高速缓存行数，并允许相对于数据高速缓存行的所需数据对齐。

公开(公告)号：US08490065B2

公开(公告)日：2013-07-16

申请号：US11250054

申请日：2005-10-13

申请人： Roch Archambault ,  Yaoqing Gao ,  Francis Patrick O'Connell ,  Robert Brett Tremaine ,  Michael Edward Wazlowski ,  Steven Wayne White ,  Lixin Zhang

发明人： Roch Archambault ,  Yaoqing Gao ,  Francis Patrick O'Connell ,  Robert Brett Tremaine ,  Michael Edward Wazlowski ,  Steven Wayne White ,  Lixin Zhang

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F9/3879 ,  G06F8/4442 ,  G06F9/30047 ,  G06F9/3455 ,  G06F12/0862 ,  G06F2212/6028

摘要： The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.

摘要翻译： 本发明提供了一种用于编译用于管理高速缓存系统的指令的计算机实现的方法，装置和计算机可用程序代码。 分析循环结构以识别指令中的缓存和预取条件的数据使用特征以形成识别的预取条件。 基于数据使用特性和识别的预取条件将一组控制指令插入到指令中以形成多个修改的指令。 编译多组修改指令的集合以生成用于执行的代码以形成编译指令。 编译指令中的一组控制指令形成高速缓存管理策略以在执行编译指令期间控制存储器系统中数据的移动。

公开(公告)号：US5860014A

公开(公告)日：1999-01-12

申请号：US729307

申请日：1996-10-15

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3861

摘要： A method and apparatus for maintaining content of registers of a processor which uses the registers for processing instructions. Entries are stored in a buffer for restoring register content in response to an interruption by an interruptible instruction. Entries include information for reducing the number of entries selected for the restoring. A set of the buffer entries is selected, in response to the interruption and the information, for restoring register content. The set includes only entries which are necessary for restoring the content in response to the interruption so that the content of the processor registers may be restored in a single processor cycle, even if multiple entries are stored for a first one of the registers and multiple entries are stored for a second one of the registers.

摘要翻译： 一种用于维护使用寄存器处理指令的处理器的寄存器的内容的方法和装置。 条目存储在缓冲器中，用于通过可中断指令中断来恢复寄存器内容。 条目包括用于减少为恢复选择的条目数量的信息。 响应于中断和信息来选择一组缓冲器条目用于恢复寄存器内容。 该集合仅包括为了响应于中断而恢复内容所必需的条目，使得处理器寄存器的内容可以在单个处理器周期中被恢复，即使对于第一个寄存器和多个条目存储了多个条目 存储在第二个寄存器中。

公开(公告)号：US5784604A

公开(公告)日：1998-07-21

申请号：US959183

申请日：1992-10-09

申请人： John Stephen Muhich ,  Terrence Matthew Potter ,  Steven Wayne White

发明人： John Stephen Muhich ,  Terrence Matthew Potter ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3804

摘要： A method and system are disclosed for reducing run-time delay during conditional branch instruction execution in a pipelined processor system. A series of queued sequential instructions and conditional branch instructions are processed wherein each conditional branch instruction specifies an associated conditional branch to be taken in response to a selected outcome of processing one or more sequential instructions. Upon detection of a conditional branch instruction within the queue, a group of target instructions are fetched based upon a prediction that an associated conditional branch will be taken. Sequential instructions within the queue following the conditional branch instruction are then purged and the target instructions loaded into the queue only in response to a successful a retrieval of the target instructions, such that the sequential instructions may be processed without delay if the prediction that the conditional branch is taken proves invalid prior to retrieval of the target instructions. Alternately, the purged sequential instructions may be refetched after loading the target instructions such that the sequential instructions may be executed with minimal delay if the prediction that the conditional branch is taken proves invalid after loading the target instructions. In yet another embodiment, the sequential instructions within the queue following the conditional branch instruction are purged only in response to a successful retrieval of the target instructions and an imminent execution of the conditional branch instruction.

摘要翻译： 公开了一种用于在流水线处理器系统中的条件分支指令执行期间减少运行时间延迟的方法和系统。 处理一系列排队的顺序指令和条件分支指令，其中每个条件分支指令响应于处理一个或多个顺序指令的所选结果来指定要采取的相关联的条件分支。 在检测到队列内的条件分支指令之后，基于将采用相关联的条件分支的预测来取得一组目标指令。 随后条件分支指令之后的队列中的顺序指令被清除，并且目标指令仅仅响应于目标指令的成功检索而被加载到队列中，使得如果预测条件 在检索目标指令之前，分支被认为是无效的。 或者，可以在加载目标指令之后重新抽取清除的顺序指令，使得如果在加载目标指令之后条件分支的预测被证明是无效的，则可以以最小延迟执行顺序指令。 在另一个实施例中，仅在响应于目标指令的成功检索和条件分支指令的即将执行之后才清除在条件分支指令之后的队列内的顺序指令。

公开(公告)号：US08037034B2

公开(公告)日：2011-10-11

申请号：US11781833

申请日：2007-07-23

申请人： Piotr M. Plachta ,  Wolfram Sauer ,  Balakrishna Raghavendra Iyer ,  Steven Wayne White

发明人： Piotr M. Plachta ,  Wolfram Sauer ,  Balakrishna Raghavendra Iyer ,  Steven Wayne White

IPC分类号： G06F7/00 ,  G06F17/00

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favors longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.

摘要翻译： 本发明的一些方面提供用于创建静态词典的方法，系统和计算机程序产品，其中优选较长的字节串。 为此，根据本发明的方面，定义新的启发式来代替用于记录数据树中的特定节点被访问次数的上述频率计数度量。 新的启发式是基于对特定字节串的端节点进行访问的次数进行计数，而不会在每次访问这些节点时频繁地在字节串中间存储字符的节点递增计数 。 结果是有利于较长字节串的发生计数度量，偏向于不增加在字节串中间存储字符的节点的相应出现计数值。

公开(公告)号：US20100287339A1

公开(公告)日：2010-11-11

申请号：US12437624

申请日：2009-05-08

申请人： Bret Ronald Olszewski ,  Steven Wayne White

发明人： Bret Ronald Olszewski ,  Steven Wayne White

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842

摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

摘要翻译： 通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联 的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及在所述新的高速缓存行条目处高速缓存所述数据，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

公开(公告)号：US6079002A

公开(公告)日：2000-06-20

申请号：US935573

申请日：1997-09-23

申请人： Larry Edward Thatcher ,  John Stephen Muhich ,  Steven Wayne White ,  Troy Neal Hicks

发明人： Larry Edward Thatcher ,  John Stephen Muhich ,  Steven Wayne White ,  Troy Neal Hicks

IPC分类号： G06F9/38 ,  G06F12/00

CPC分类号： G06F9/3867 ,  G06F9/3824

摘要： A method and system in a data processing system for accessing information using an instruction specifying a memory address is disclosed. The method and system comprises issuing the instruction to an execution unit and storing an address derived from the specified address. The method and system also includes accessing a cache to obtain the information, using the derived address and determining, in response to a signal indicating that there has been a cache miss, if there is a location available to store the specified address in a queue. According to the system and method disclosed herein, the present invention allows for dynamic pipeline expansion of a processor without splitting this function between components depending upon the reason expansion was required, thereby increasing overall system performance.

摘要翻译： 公开了一种使用指定存储器地址的指令访问信息的数据处理系统中的方法和系统。 该方法和系统包括向执行单元发出指令并存储从指定地址导出的地址。 该方法和系统还包括访问高速缓存以获得信息，使用导出的地址并且响应于指示已经存在高速缓存未命中的信号确定是否存在可用于将指定的地址存储在队列中的位置。 根据本文公开的系统和方法，根据需要扩展的原因，本发明允许处理器的动态管道扩展，而不会在组件之间分离该功能，从而提高整体系统性能。

公开(公告)号：US08458401B2

公开(公告)日：2013-06-04

申请号：US13398443

申请日：2012-02-16

申请人： Bret Ronald Olszewski ,  Steven Wayne White

发明人： Bret Ronald Olszewski ,  Steven Wayne White

IPC分类号： G06F12/08

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842

摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein the shared cache memory is effectively shared on a line-by-line basis among the plurality of logical processing partitions of the multi-core processor.

摘要翻译： 通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联 的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及将所述数据缓存在所述新的高速缓存行条目上，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

公开(公告)号：US08447929B2

公开(公告)日：2013-05-21

申请号：US13398292

申请日：2012-02-16

申请人： Bret Ronald Olszewski ,  Steven Wayne White

发明人： Bret Ronald Olszewski ,  Steven Wayne White

IPC分类号： G06F15/16

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842

摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

摘要翻译： 通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联 的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及在所述新的高速缓存行条目处高速缓存所述数据，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。