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1.发明授权公开(公告)号：US06288712B1
公开(公告)日：2001-09-11
申请号：US08970665
申请日：1997-11-14
IPC分类号： G09G500
CPC分类号： G09G3/3648
摘要： A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.
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公开(公告)号：US20120086733A1
公开(公告)日：2012-04-12
申请号：US13252356
申请日：2011-10-04
CPC分类号： G09G3/3648 , G09G2300/0857 , G09G2320/0209 , G09G2320/0247 , G09G2320/0261 , G09G2330/026
摘要： A display system which includes a display controller, a display unit, and a light source is disclosed. The display controller includes a processor unit, a memory device, a voltage source and, optionally, a light source control unit. The display unit includes an array of pixel cells and circuitry to receive logic and control voltages and data and operate the display, a transparent counter electrode, and a liquid crystal layer disposed between the two alignment layers. The pixel cell includes a storage element, a DC balance control switch, a pixel voltage override circuit, an inverter able to select between two voltages available to it, and a pixel electrode/mirror. In different modes of operation the pixel mirror voltage may be determined by the storage element or by the pixel voltage override circuit. The display system may display images in one period and reset to a fixed state in another period.
摘要翻译： 公开了一种包括显示控制器，显示单元和光源的显示系统。 显示控制器包括处理器单元，存储器件，电压源和可选的光源控制单元。 显示单元包括像素单元阵列和用于接收逻辑和控制电压和数据并操作显示器，透明对电极和布置在两个取向层之间的液晶层的电路。 像素单元包括存储元件，DC平衡控制开关，像素电压覆盖电路，能够在其可用的两个电压之间进行选择的反相器和像素电极/反射镜。 在不同的操作模式中，像素反射镜电压可由存储元件或像素电压覆盖电路确定。 显示系统可以在一个周期内显示图像并在另一个周期中重置为固定状态。
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3.发明授权Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit 失效内部行排序器，用于降低显示驱动电路中的带宽和峰值电流要求公开(公告)号：US06188377B1
公开(公告)日：2001-02-13
申请号：US09047947
申请日：1998-03-25
IPC分类号： G09G336
CPC分类号： G09G3/2085 , G09G3/20 , G09G3/3659 , G09G2300/0842 , G09G2300/0857 , G09G2310/02 , G09G2310/0221 , G09G2310/0254 , G09G2310/0262 , G09G2310/0267 , G09G2310/027 , G09G2310/0275 , G09G2330/025 , G09G2370/08
摘要： A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals. In various embodiments, the row sequencer, the sub-row sequencer, and/or the data path sequencer is/are responsive to data load instructions from a system, such that no Array Write commands are required to write data to a display.
摘要翻译： 显示驱动器电路包括用于提供一系列行地址的字线序列发生器，以及行解码器，用于解码每个行地址，并在多个输出端上对应的一个输出端确定写入信号。 可选的数据路径定序器提供一系列路由地址，这些路由地址由可选数据路由器用于将数据路由到显示器的特定子行。 此外，可选的子行排序器向可选的子行解码器提供一系列子行地址，该子行解码器对每个子行地址进行解码，并且在第二多个输出终端的对应的一个输出终端上确定写入信号。 在各种实施例中，行排序器，子行排序器和/或数据路径定序器响应于来自系统的数据加载指令，使得不需要阵列写入命令来将数据写入显示器。
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公开(公告)号：US08760477B2
公开(公告)日：2014-06-24
申请号：US13252356
申请日：2011-10-04
IPC分类号： G09G5/10
CPC分类号： G09G3/3648 , G09G2300/0857 , G09G2320/0209 , G09G2320/0247 , G09G2320/0261 , G09G2330/026
摘要： A display system which includes a display controller, a display unit, and a light source is disclosed. The display controller includes a processor unit, a memory device, a voltage source and, optionally, a light source control unit. The display unit includes an array of pixel cells and circuitry to receive logic and control voltages and data and operate the display, a transparent counter electrode, and a liquid crystal layer disposed between the two alignment layers. The pixel cell includes a storage element, a DC balance control switch, a pixel voltage override circuit, an inverter able to select between two voltages available to it, and a pixel electrode/mirror. In different modes of operation the pixel mirror voltage may be determined by the storage element or by the pixel voltage override circuit. The display system may display images in one period and reset to a fixed state in another period.
摘要翻译： 公开了一种包括显示控制器，显示单元和光源的显示系统。 显示控制器包括处理器单元，存储器件，电压源和可选的光源控制单元。 显示单元包括像素单元阵列和用于接收逻辑和控制电压和数据并操作显示器，透明对电极和布置在两个取向层之间的液晶层的电路。 像素单元包括存储元件，DC平衡控制开关，像素电压覆盖电路，能够在其可用的两个电压之间进行选择的反相器和像素电极/反射镜。 在不同的操作模式中，像素反射镜电压可由存储元件或像素电压覆盖电路确定。 显示系统可以在一个周期内显示图像并在另一个周期中重置为固定状态。
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5.发明授权Display with multiplexed pixels for achieving modulation between saturation and threshold voltages 失效显示多路复用像素，以实现饱和电压和阈值电压之间的调制
公开(公告)号：US6005558A
公开(公告)日：1999-12-21
申请号：US75124
申请日：1998-05-08
CPC分类号： G09G3/3696 , G09G3/3614 , G09G2300/0804 , G09G2300/0809 , G09G2300/0842 , G09G2320/0204 , G09G3/2018 , G09G3/2022
摘要： A display includes a pair of global voltage supply terminals, for providing predetermined voltages, and a plurality of pixel cells. Each pixel cell includes a pixel electrode, a storage element for storing a data bit, and a multiplexer for selectively coupling the pixel electrode with one or the other of the global voltage supply terminals, depending on the value of the stored data bit. A voltage controller asserts predetermined voltages on the global voltage supply terminals, which are then transferred to the coupled pixel electrodes.
摘要翻译： 显示器包括用于提供预定电压的一对全局电压源端子和多个像素单元。 每个像素单元包括像素电极，用于存储数据位的存储元件以及根据存储的数据位的值选择性地将像素电极与全局电压源端子中的一个或另一个耦合的多路复用器。 电压控制器在全局电压源端子上断定预定的电压，然后传送到耦合的像素电极。
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