公开(公告)号：US20200313883A1

公开(公告)日：2020-10-01

申请号：US16805815

申请日：2020-03-01

申请人： Realtek Semiconductor Corp.

发明人： Kuan-Chia Huang ,  Tsung-Hsuan Wu ,  Ching-Sheng Cheng

IPC分类号： H04L9/12 ,  G06F3/14

摘要： A receiving circuit includes a first channel, a second channel, a third channel and a control circuit, wherein the first channel is arranged to decode and descramble a first data stream to generate first data corresponding to first color information of an image frame, the second channel is arranged to decode and descramble a second data stream to generate second data corresponding to second color information of the image frame, and the third channel is arranged to decode and descramble a third data stream to generate third data corresponding to third color information of the image frame. The control circuit is configured to enable the first channel to make the first channel decode the first data stream, and enable or disable at least part of functions of the second channel and the third channel according to whether or not the image frame is displayed on a display panel.

公开(公告)号：US20160013938A1

公开(公告)日：2016-01-14

申请号：US14793734

申请日：2015-07-07

申请人： Realtek Semiconductor Corp.

发明人： Ching-Sheng Cheng ,  Kuan-Chia Huang

IPC分类号： H04L9/08 ,  H04L9/06

CPC分类号： H04L9/0637 ,  H04L9/0891 ,  H04L9/12

摘要： A decryption engine includes an update circuit, a key generator, a decryption circuit and a detection circuit. The update circuit generates a first updating information based on a premise of that a currently received frame is encrypted, and generates a second updating information based on a premise of that the currently received frame is non-encrypted. The key generator produces a first key according to the first updating information, and produces a second key according to the second updating information. The decryption circuit generates a first decrypted frame according to the first key and the currently received frame, and generates a second decrypted frame according to the second key and the currently received frame. The detection circuit detects whether the currently received frame is decrypted according to the first decrypted frame and the second decrypted frame, to generate an encryption detection result.

摘要翻译： 解密引擎包括更新电路，密钥生成器，解密电路和检测电路。 更新电路基于当前接收到的帧被加密的前提产生第一更新信息，并且基于当前接收到的帧未被加密的前提生成第二更新信息。 密钥发生器根据第一更新信息产生第一密钥，并根据第二更新信息产生第二密钥。 解密电路根据第一密钥和当前接收到的帧生成第一解密帧，并根据第二密钥和当前接收的帧生成第二解密帧。 检测电路根据第一解密帧和第二解密帧来检测当前接收到的帧是否被解密，以产生加密检测结果。

公开(公告)号：US11048651B2

公开(公告)日：2021-06-29

申请号：US16744202

申请日：2020-01-16

申请人： Realtek Semiconductor Corp.

发明人： Ching-Sheng Cheng ,  Wen-Wei Lin ,  Kuan-Chia Huang

IPC分类号： G06F13/16 ,  G11C11/4076 ,  G11C8/18 ,  G06F12/02

摘要： A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices is disclosed. The method comprises assigning a first operation timing to a first memory controller of the plurality of memory controllers and assigning a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing is interleaved with the time of the second operation timing, transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices, and transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices.

公开(公告)号：US20210173566A1

公开(公告)日：2021-06-10

申请号：US16876097

申请日：2020-05-17

申请人： Realtek Semiconductor Corp.

发明人： Ching-Sheng Cheng ,  Wen-Wei Lin ,  Kuan-Chia Huang

IPC分类号： G06F3/06 ,  G06F1/08

摘要： A control method of a memory system is disclosed. The memory system includes a controller, an interface and a memory. The interface is coupled to the controller, and the memory is coupled to the controller through the interface. The control method includes the controller sending a clock signal to the memory through the interface, and the controller sending an access command to the memory through the interface to access data at an access address of the memory. The clock signal has a clock period. A time span for the controller to send the access command to the memory is substantially 1.5 clock periods.

公开(公告)号：US20210026789A1

公开(公告)日：2021-01-28

申请号：US16744202

申请日：2020-01-16

申请人： Realtek Semiconductor Corp.

发明人： Ching-Sheng Cheng ,  Wen-Wei Lin ,  Kuan-Chia Huang

IPC分类号： G06F13/16 ,  G06F12/02 ,  G11C8/18 ,  G11C11/4076

摘要： A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices is disclosed. The method comprises assigning a first operation timing to a first memory controller of the plurality of memory controllers and assigning a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing is interleaved with the time of the second operation timing, transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices, and transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices.

公开(公告)号：US11411729B2

公开(公告)日：2022-08-09

申请号：US16805815

申请日：2020-03-01

申请人： Realtek Semiconductor Corp.

发明人： Kuan-Chia Huang ,  Tsung-Hsuan Wu ,  Ching-Sheng Cheng

IPC分类号： G06F3/14 ,  H04L9/12

摘要： A receiving circuit includes a first channel, a second channel, a third channel and a control circuit, wherein the first channel is arranged to decode and descramble a first data stream to generate first data corresponding to first color information of an image frame, the second channel is arranged to decode and descramble a second data stream to generate second data corresponding to second color information of the image frame, and the third channel is arranged to decode and descramble a third data stream to generate third data corresponding to third color information of the image frame. The control circuit is configured to enable the first channel to make the first channel decode the first data stream, and enable or disable at least part of functions of the second channel and the third channel according to whether or not the image frame is displayed on a display panel.

公开(公告)号：US11321232B2

公开(公告)日：2022-05-03

申请号：US16856059

申请日：2020-04-23

申请人： Realtek Semiconductor Corp.

发明人： Wen-Wei Lin ,  Kuan-Chia Huang ,  Ching-Sheng Cheng

IPC分类号： G11C11/408 ,  G06F12/06

摘要： A method for simultaneously accessing a first DRAM device and a second DRAM device includes the steps of: in an active phase, generating a first signal at a first pad, wherein the first signal is provided for the first DRAM device to select a first memory bank group, and the first signal is not for the second DRAM device to select any memory bank group; and generating a second signal at the first pad, wherein the second signal is provided for the first DRAM device to select the first bank group, and the second signal and the first signal correspond to a same digital value.

公开(公告)号：US20210271616A1

公开(公告)日：2021-09-02

申请号：US17169520

申请日：2021-02-07

申请人： Realtek Semiconductor Corp.

发明人： Ching-Sheng Cheng ,  Wen-Wei Lin ,  Kuan-Chia Huang

IPC分类号： G06F13/16

摘要： The present invention provides a control method of multiple memory devices, wherein the multiple devices comprise a first memory device and a second memory device, and the control method includes the steps of: determining a first operation timing and a second operation timing according to at least a first command signal that a first memory controller needs to send to the first memory device; controlling the first memory controller to send the first command signal to the first memory device at the first operation timing; and controlling the second memory controller to send the second command signal to the second memory device at the second operation timing.

公开(公告)号：US09774444B2

公开(公告)日：2017-09-26

申请号：US14793734

申请日：2015-07-07

申请人： Realtek Semiconductor Corp.

发明人： Ching-Sheng Cheng ,  Kuan-Chia Huang

IPC分类号： H04L9/08 ,  H04L9/06 ,  H04L9/12

CPC分类号： H04L9/0637 ,  H04L9/0891 ,  H04L9/12

摘要： A decryption engine includes an update circuit, a key generator, a decryption circuit and a detection circuit. The update circuit generates a first updating information based on a premise of that a currently received frame is encrypted, and generates a second updating information based on a premise of that the currently received frame is non-encrypted. The key generator produces a first key according to the first updating information, and produces a second key according to the second updating information. The decryption circuit generates a first decrypted frame according to the first key and the currently received frame, and generates a second decrypted frame according to the second key and the currently received frame. The detection circuit detects whether the currently received frame is decrypted according to the first decrypted frame and the second decrypted frame, to generate an encryption detection result.