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公开(公告)号：US11694743B2
公开(公告)日：2023-07-04
申请号：US17340062
申请日：2021-06-06
发明人： Ching-Sheng Cheng
IPC分类号： G11C16/04 , G11C11/408 , G06F13/42
CPC分类号： G11C11/408 , G06F13/4221
摘要： A chip system includes a first chip, a first DRAM, a second chip and a second DRAM. The first chip includes a first DRAM controller and a first serial transmission interface. The first DRAM is coupled to the first DRAM controller. The second chip includes a second DTAM controller and a second serial transmission interface. The second serial transmission interface is coupled to the first serial transmission interface. The second DRAM is coupled to the second DRAM controller. When the first chip intends to store first data and second data, the first chip stores the first data into the first DRAM via the first DRAM controller, and transmits the second data to the second chip via the first serial transmission interface; and the second chip stores the second data into the second DRAM via the second DRAM controller.
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公开(公告)号：US20220068344A1
公开(公告)日：2022-03-03
申请号：US17340062
申请日：2021-06-06
发明人： Ching-Sheng Cheng
IPC分类号： G11C11/408 , G06F13/42
摘要： A chip system includes a first chip, a first DRAM, a second chip and a second DRAM. The first chip includes a first DRAM controller and a first serial transmission interface. The first DRAM is coupled to the first DRAM controller. The second chip includes a second DRAM controller and a second serial transmission interface. The second serial transmission interface is coupled to the first serial transmission interface. The second DRAM is coupled to the second DRAM controller. When the first chip intends to store first data and second data, the first chip stores the first data into the first DRAM via the first DRAM controller, and transmits the second data to the second chip via the first serial transmission interface; and the second chip stores the second data into the second DRAM via the second DRAM controller.
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3.发明申请公开(公告)号：US20200313883A1
公开(公告)日：2020-10-01
申请号：US16805815
申请日：2020-03-01
摘要： A receiving circuit includes a first channel, a second channel, a third channel and a control circuit, wherein the first channel is arranged to decode and descramble a first data stream to generate first data corresponding to first color information of an image frame, the second channel is arranged to decode and descramble a second data stream to generate second data corresponding to second color information of the image frame, and the third channel is arranged to decode and descramble a third data stream to generate third data corresponding to third color information of the image frame. The control circuit is configured to enable the first channel to make the first channel decode the first data stream, and enable or disable at least part of functions of the second channel and the third channel according to whether or not the image frame is displayed on a display panel.
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4.发明申请公开(公告)号：US20200312276A1
公开(公告)日：2020-10-01
申请号：US16808403
申请日：2020-03-04
发明人： Tsung-Hsuan Wu , Hsu-Jung Tung , Ching-Sheng Cheng
摘要： The present invention provides a receiving circuit applied to an HDMI, wherein the receiving circuit includes a decoder, a frame key calculating circuit, a line key calculating circuit and a control circuit. In the operations of the receiving circuit, the decoder decodes a data stream to generate at least one image frame, the frame key calculating circuit is arranged to calculate a frame key according to the image frame, the line key calculating circuit is arranged to calculate a plurality of line keys according to the image frame, and the control circuit determines to turn off or turn on the line key calculating circuit according to whether or not the image frame is displayed on a display panel.
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公开(公告)号：US09007107B2
公开(公告)日：2015-04-14
申请号：US14207496
申请日：2014-03-12
发明人： Ching-Sheng Cheng , Chao-Yang Tsai
摘要： A signal generating circuit comprises a signal synchronizing module and a control circuit. The signal synchronizing module includes: a first delay path for delaying a target signal to generate a first delayed target signal by utilizing a first delay amount; a second delay path for delaying the target signal to generate a second delayed target signal by utilizing a second delay amount larger than the first delay amount; and a logic module, for gating the target signal to generate a first output signal according to the first delayed target signal, or gating the target signal to generate a second output signal according to the second delayed target signal. The control circuit controls the signal synchronizing module to output one of the first output signal and the second output signal according to phase difference between the target signal and a reference signal.
摘要翻译： 信号发生电路包括信号同步模块和控制电路。 信号同步模块包括：第一延迟路径，用于通过利用第一延迟量来延迟目标信号以产生第一延迟目标信号; 第二延迟路径，用于通过利用大于第一延迟量的第二延迟量来延迟目标信号以产生第二延迟目标信号; 以及逻辑模块，用于选通所述目标信号以根据所述第一延迟目标信号产生第一输出信号，或选通所述目标信号，以根据所述第二延迟目标信号产生第二输出信号。 控制电路控制信号同步模块根据目标信号和参考信号之间的相位差输出第一输出信号和第二输出信号中的一个。
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公开(公告)号：US20210173566A1
公开(公告)日：2021-06-10
申请号：US16876097
申请日：2020-05-17
发明人： Ching-Sheng Cheng , Wen-Wei Lin , Kuan-Chia Huang
摘要： A control method of a memory system is disclosed. The memory system includes a controller, an interface and a memory. The interface is coupled to the controller, and the memory is coupled to the controller through the interface. The control method includes the controller sending a clock signal to the memory through the interface, and the controller sending an access command to the memory through the interface to access data at an access address of the memory. The clock signal has a clock period. A time span for the controller to send the access command to the memory is substantially 1.5 clock periods.
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公开(公告)号：US20210026789A1
公开(公告)日：2021-01-28
申请号：US16744202
申请日：2020-01-16
发明人： Ching-Sheng Cheng , Wen-Wei Lin , Kuan-Chia Huang
IPC分类号： G06F13/16 , G06F12/02 , G11C8/18 , G11C11/4076
摘要： A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices is disclosed. The method comprises assigning a first operation timing to a first memory controller of the plurality of memory controllers and assigning a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing is interleaved with the time of the second operation timing, transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices, and transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices.
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公开(公告)号：US08896350B2
公开(公告)日：2014-11-25
申请号：US14064553
申请日：2013-10-28
发明人： Ching-Sheng Cheng , Hsu-Jung Tung
IPC分类号： G11C27/02
CPC分类号： H03K5/159
摘要： A sampling circuit and a sampling method are provided, where the sampling circuit includes a first delay chain, a second delay chain, and a half-speed binary-phase detector. The first delay chain is used to delay an input signal according to an up signal and a down signal, so as to generate a first delay signal; and the second delay chain is used to delay the first delay signal according to a preset delay value, so as to generate a second delay signal. The half-speed binary-phase detector is used to sample a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate an output signal, an up signal, and a down signal according to a sampling result of the data signal.
摘要翻译： 提供采样电路和采样方法，其中采样电路包括第一延迟链，第二延迟链和半速二进制相位检测器。 第一延迟链用于根据上升信号和下降信号延迟输入信号，以产生第一延迟信号; 并且第二延迟链用于根据预设的延迟值来延迟第一延迟信号，以便产生第二延迟信号。 半速二进制相位检测器用于根据第一延迟信号和第二延迟信号的边沿触发采样数据信号，并根据采样产生输出信号，上升信号和下降信号 数据信号的结果。
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公开(公告)号：US20240205443A1
公开(公告)日：2024-06-20
申请号：US18237380
申请日：2023-08-23
发明人： Wun-Lin Chang , Pui-Kei Leong , Ching-Sheng Cheng
IPC分类号： H04N19/46 , H04N21/4363
CPC分类号： H04N19/46 , H04N21/43635
摘要： An electronic device includes a decoder circuit, an image processing circuit, a detection circuit, a transmission interval determination circuit, an auxiliary data extraction circuit, and an encoder circuit. The decoder circuit decodes an input signal to generate the decoded signal. The image processing circuit performs image processing on the decoded signal to generate processed image data. The detection circuit detects timing of an active display area and a vertical synchronization signal in the processed image data to generate a detection result. The transmission interval determination circuit determines a transmission interval of the processed image data according to the detection result. The auxiliary data extraction circuit extracts auxiliary data from the decoded signal. The encoder circuit places the auxiliary data in the transmission interval of the processed image data, and performs encoding to generate an output signal.
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公开(公告)号：US11411729B2
公开(公告)日：2022-08-09
申请号：US16805815
申请日：2020-03-01
摘要： A receiving circuit includes a first channel, a second channel, a third channel and a control circuit, wherein the first channel is arranged to decode and descramble a first data stream to generate first data corresponding to first color information of an image frame, the second channel is arranged to decode and descramble a second data stream to generate second data corresponding to second color information of the image frame, and the third channel is arranged to decode and descramble a third data stream to generate third data corresponding to third color information of the image frame. The control circuit is configured to enable the first channel to make the first channel decode the first data stream, and enable or disable at least part of functions of the second channel and the third channel according to whether or not the image frame is displayed on a display panel.
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