公开(公告)号：US20240007208A1

公开(公告)日：2024-01-04

申请号：US17938050

申请日：2022-10-05

申请人： Realtek Semiconductor Corporation

发明人： Shih-Chang CHEN ,  Chih-Wei CHANG ,  Chun-Chi YU

IPC分类号： H04B17/345

CPC分类号： H04B17/345

摘要： An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.

公开(公告)号：US20230126654A1

公开(公告)日：2023-04-27

申请号：US17507864

申请日：2021-10-22

申请人： Realtek Semiconductor Corporation

发明人： Chun-Chi YU ,  Chih-Wei CHANG ,  Gerchih CHOU

IPC分类号： G06F3/06 ,  G11C11/4076 ,  G06F1/06

摘要： A processor circuit sends a read request. A clock signal of the processor circuit corresponds to a first counting value. A memory circuit stores data and sends a data strobe signal in response to the read request. The data strobe signal corresponds to a second counting value. The processor circuit includes a selector circuit and a feedback circuit. The selector circuit selects and outputs a flag signal from a plurality of flag control signals according to the second counting value. The feedback circuit generates an enable signal according to a set signal associated with the first counting value, the flag signal associated with the second counting value, and a data strobe gate signal, and generates the data strobe gate signal according to the enable signal and the data strobe signal. The processor circuit reads the data according to the data strobe gate signal.

公开(公告)号：US20180233211A1

公开(公告)日：2018-08-16

申请号：US15894844

申请日：2018-02-12

申请人： Realtek Semiconductor Corporation

发明人： Chun-Chi YU ,  Chih-Wei CHANG ,  Shen-Kuo HUANG

IPC分类号： G11C29/02 ,  G11C11/4076 ,  G11C29/50 ,  G11C11/409

CPC分类号： G11C29/025 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/409 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

摘要： A memory test method is provided that includes the steps outlined below. The memory controller performs data-writing and data-reading on a memory module. When a quantity of read data is incorrect, a data-strobe enable signal is calibrated to perform data reading. When there is one of less than one piece of negative edge data reading content, a sampling unit is triggered. When the quantity of read data increases, the condition that the data-strobe signal is not received is determined. When the quantity does not increase, the memory controller is inspected. When there is more than one piece of read data, the burst mode setting of the memory module is inspected. When the quantity is correct and the content is not correct, a transmission circuit setting and the sampling unit are inspected. When the quantity and the content are correct, the test flow is terminated.

公开(公告)号：US20160329085A1

公开(公告)日：2016-11-10

申请号：US15093758

申请日：2016-04-08

申请人： Realtek Semiconductor Corporation

发明人： Chun-Chi YU ,  Chih-Wei CHANG ,  Gerchih CHOU ,  Fu-Chin TSAI ,  Shih-Chang CHEN

IPC分类号： G11C7/22

CPC分类号： G11C7/222 ,  G11C7/22

摘要： A memory physical layer interface circuit electrically connected between a memory controller and a memory device is provided. The memory physical layer interface circuit includes a dock generation module and first-in-first-out (FIFO) modules. The clock generation module generates a reference clock signal and output related clock signals. The reference clock signal is transmitted to the memory device. Each of the FIFO modules writes the input information therein transmitted by the memory controller according to a write-related clock signal and retrieves the input information therefrom according to one of the output related clock signals to generate an output signal. The output signal is transmitted to the memory device to operate the memory device. The write-related clock signal is generated by dividing a frequency of one of the output related clock signals.

摘要翻译： 提供电连接在存储器控制器和存储器件之间的存储器物理层接口电路。 存储器物理层接口电路包括坞站生成模块和先进先出（FIFO）模块。 时钟产生模块产生参考时钟信号并输出​​相关的时钟信号。 参考时钟信号被发送到存储器件。 每个FIFO模块根据写相关的时钟信号将存储器控制器发送的输入信息写入其中，并根据输出相关时钟信号之一检索输入信息，以产生输出信号。 输出信号被传送到存储器件以操作存储器件。 写相关时钟信号是通过除去输出相关时钟信号之一的频率而产生的。