公开(公告)号：US10103226B2

公开(公告)日：2018-10-16

申请号：US13459278

申请日：2012-04-30

申请人： Reinaldo A. Vega ,  Emre Alptekin ,  Hung H. Tran ,  Xiaobin Yuan

发明人： Reinaldo A. Vega ,  Emre Alptekin ,  Hung H. Tran ,  Xiaobin Yuan

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L21/28

摘要： A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.

公开(公告)号：US20130285138A1

公开(公告)日：2013-10-31

申请号：US13459278

申请日：2012-04-30

申请人： Reinaldo A. Vega ,  Emre Alptekin ,  Hung H. Tran ,  Xiaobin Yuan

发明人： Reinaldo A. Vega ,  Emre Alptekin ,  Hung H. Tran ,  Xiaobin Yuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0684 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/78

摘要： A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.

摘要翻译： 制造隧道场效应晶体管（TFET）的方法包括在由外延生长的源材料覆盖的衬底上形成由侧壁间隔物包围的虚拟栅极堆叠; 形成掺杂源极和漏极区域，随后形成围绕侧壁间隔物的层间电介质; 去除虚拟栅极堆叠，蚀刻自对准腔; 在自对准蚀刻腔内外延生长薄沟道区; 在自对准的蚀刻腔内共形沉积栅极电介质和金属栅极材料; 并且平坦化替代金属栅极堆叠的顶表面以去除栅极电介质和金属栅极材料的残留物。

公开(公告)号：US20120190160A1

公开(公告)日：2012-07-26

申请号：US13428061

申请日：2012-03-23

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L21/335

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

公开(公告)号：US20120007145A1

公开(公告)日：2012-01-12

申请号：US12831310

申请日：2010-07-07

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L29/165 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

摘要翻译： 场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。 通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

公开(公告)号：US08298897B2

公开(公告)日：2012-10-30

申请号：US13428061

申请日：2012-03-23

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

公开(公告)号：US08237197B2

公开(公告)日：2012-08-07

申请号：US12831310

申请日：2010-07-07

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L29/66

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

摘要翻译： 场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。 通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。