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48 条记录 (耗时 0.027 秒)

    Leakage power management using programmable power gating transistors and on-chip aging and temperature tracking circuit
    4.
    发明授权
    Leakage power management using programmable power gating transistors and on-chip aging and temperature tracking circuit 有权
    漏电功率管理采用可编程电源门控晶体管和片上老化和温度跟踪电路

    公开(公告)号：US08736314B2

    公开(公告)日：2014-05-27

    申请号：US13053374

    申请日：2011-03-22

    申请人： Nam Sung Kim

    发明人： Nam Sung Kim

    IPC分类号： H03K3/00

    CPC分类号： H03K19/0016

    摘要： The number of power-gating transistors on an integrated circuit used for power reduction in a sleep mode is controlled during a wake state to adjust the current flow and hence voltage drop across the power-gating transistors as a function of aging of these transistors and/or a function of temperature of the integrated circuit. In this way, the supply voltage to the integrated circuit may be better tailored to minimize current leakage when the integrated circuit is young or operating at low temperatures.

    摘要翻译： 在休眠模式下用于功率降低的集成电路上的功率门控晶体管的数量在唤醒状态期间被控制，以调节电流流动，并因此调节功率门控晶体管上的电压降，这是这些晶体管的老化和/ 或集成电路的温度的函数。 以这种方式，集成电路的电源电压可以被更好地定制，以在集成电路较小或在低温下工作时最小化电流泄漏。

    Method and apparatus improving performance of a digital memory array device
    7.
    发明申请
    Method and apparatus improving performance of a digital memory array device 审中-公开
    提高数字存储器阵列器件性能的方法和装置

    公开(公告)号：US20090006742A1

    公开(公告)日：2009-01-01

    申请号：US11823358

    申请日：2007-06-27

    申请人： Min Huang ,  Chris Wilkerson ,  Nam Sung Kim ,  Moinuddin K. Qureshi

    发明人： Min Huang ,  Chris Wilkerson ,  Nam Sung Kim ,  Moinuddin K. Qureshi

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0893 ,  G06F2212/1032 ,  G11C7/1006 ,  G11C11/413

    摘要： A method for improving performance of a digital memory array device including a plurality of memory cells; each respective memory cell storing a first digital value and a second digital value being an inverse of the first digital value; storing of the first and second digital values being controlled by a first digital signal effecting selection of a specified memory cell for storing; includes: (a) determining an extant value relating to the first digital signal; (b) if the extant value has a first value, effecting a bit flip operation in the specified memory cell to invert values of at least one of the stored first digital and the second digital values; (c) if the extant value does not have the first value, foregoing the bit flip operation in the specified memory cell.

    摘要翻译： 一种用于提高包括多个存储单元的数字存储器阵列器件的性能的方法; 每个相应的存储单元存储第一数字值，而第二数字值是第一数字值的倒数; 第一数字值和第二数字值的存储由第一数字信号控制，第一数字信号执行用于存储的指定存储单元的选择; 包括：（a）确定与第一数字信号相关的现有值; （b）如果现有值具有第一值，则在指定的存储器单元中进行位翻转操作以反转所存储的第一数字和第二数字值中的至少一个的值; （c）如果现存值不具有第一值，则前述指定存储单元中的位翻转操作。

    MOSFET transistor with thick and thin pad oxide films
    10.
    发明授权
    MOSFET transistor with thick and thin pad oxide films 失效
    MOSFET晶体管采用厚薄薄的氧化膜

    公开(公告)号：US06740943B2

    公开(公告)日：2004-05-25

    申请号：US10224490

    申请日：2002-08-21

    申请人： Nam-Sung Kim

    发明人： Nam-Sung Kim

    IPC分类号： H01L31119

    CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/7833 ,  Y10S438/981

    摘要： A MOS transistor and a method for fabricating the MOS transistor which includes the forming a gate electrode containing an HLD film; etching the HLD film; etching a pad oxide film formed at a lower portion of the HLD film at a predetermined thickness; removing the nitride side wall spacer of an opening in the gate electrode; forming a LDD region by implanting impurity ions into the semiconductor substrate at both sides of the gate electrode; forming a side wall spacer at both sides of the gate electrode; and forming a source/drain by implanting impurity ions into the semiconductor substrate.

    摘要翻译： 一种MOS晶体管及其制造方法，包括：形成含有HLD膜的栅电极; 蚀刻HLD膜; 以预定厚度蚀刻形成在HLD膜的下部的衬垫氧化膜; 去除栅电极中的开口的氮化物侧壁间隔物; 通过在栅电极的两侧将杂质离子注入到半导体衬底中来形成LDD区; 在栅电极的两侧形成侧壁间隔物; 以及通过将杂质离子注入到半导体衬底中形成源极/漏极。