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公开(公告)号：US06829554B2
公开(公告)日：2004-12-07
申请号：US10109545
申请日：2002-03-28
IPC分类号： G01K500
CPC分类号： G11C29/50 , G11C29/006
摘要： A method for classifying semiconductor components by their performance characteristics includes reading an identifier associated with a component and storing, in conjunction with the identifier, first and second performances values for that component. These performance values represent the component's achieved operating speed at each of two different temperatures. The component is then allocated to a speed category on the basis of the first and second performance values.
摘要翻译： 通过其性能特征对半导体组件进行分类的方法包括读取与组件相关联的标识符，并与该标识符一起存储该组件的第一和第二性能值。 这些性能值代表组件在两个不同温度下的实现运行速度。 然后基于第一和第二性能值将组件分配给速度类别。
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公开(公告)号：US07065687B2
公开(公告)日：2006-06-20
申请号：US10253465
申请日：2002-09-24
摘要： A method for replacing defective memory cells of a random access memory device of a data processing apparatus, in which, during the operation of the data processing apparatus, a defective memory cell is replaced by a replacement memory cell in the random access memory device by using a control instruction.
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3.发明授权Method for integrating imperfect semiconductor memory devices in data processing apparatus 有权在数据处理装置中集成不完美的半导体存储器件的方法公开(公告)号：US06762965B2
公开(公告)日：2004-07-13
申请号：US10254694
申请日：2002-09-25
IPC分类号： G11C700
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A method for integrating imperfect semiconductor memory devices having functional and defective memory cells into a data processing apparatus. The defective memory cells are assigned defect addresses or defect address ranges. Before a memory access of the data processing apparatus is carried out, the address of the memory access is compared with the defect addresses or defect address ranges and is recoded in the event of correspondence.
摘要翻译： 一种用于将具有功能和缺陷存储器单元的不完美半导体存储器件集成到数据处理装置中的方法。 缺陷存储单元被分配缺陷地址或缺陷地址范围。 在执行数据处理装置的存储器访问之前，将存储器访问的地址与缺陷地址或缺陷地址范围进行比较，并且在对应的情况下被重新编码。
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4.发明授权Method for storing data in a memory device with the possibility of access to redundant memory cells 有权将数据存储在具有访问冗余存储单元的可能性的存储器件中的方法公开(公告)号：US06819606B2
公开(公告)日：2004-11-16
申请号：US10339031
申请日：2003-01-09
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： A method is provided for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns. The method can include a step for providing redundant memory cells in the memory device. The method can also include a step for localizing defective cells. Further, the method can include a step of accessing the redundant memory cells by means of a predeterminable access mode. The method can also include a step of bypassing defective memory cells of the memory device in a manner dependent on the predeterminable access mode during operation of the memory device for accessing redundant memory cells and for replacement by redundant memory cells. Further, the method can include a step for providing redundant memory cells for storing additional information describing a defect correction.
摘要翻译： 提供了一种用于将数据存储在具有布置在存储单元行和存储单元列中的存储单元的存储器件中的方法。 该方法可以包括在存储器件中提供冗余存储器单元的步骤。 该方法还可以包括用于定位缺陷单元的步骤。 此外，该方法可以包括通过可预定访问模式访问冗余存储器单元的步骤。 该方法还可以包括在存储器设备的操作期间以取决于可预定访问模式的方式绕过存储器件的有缺陷的存储单元的步骤，用于访问冗余存储器单元并由冗余存储器单元替换。 此外，该方法可以包括用于提供用于存储描述缺陷校正的附加信息的冗余存储器单元的步骤。
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5.发明授权公开(公告)号：US06806121B2
公开(公告)日：2004-10-19
申请号：US10285090
申请日：2002-10-31
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an interconnect structure for an integrated circuit (1) having a first interconnect (B1; B1′; B1″), which is composed of a plurality of interconnect sections (A11-A16; A11′-A16′; A11″-A14″) lying in a first and a second interconnect plane (M0, M1); and a second interconnect (B2; B2′; B2″), which runs adjacent to the first interconnect (B1; B1′; B1″) and which is composed of a plurality of interconnect sections (A21-A25; A21′-A25′; A21″-A23″) lying in the first and second interconnect planes (M0, M1); the first and second interconnects (B1; B1′; B1″; B2; B2′; B2″) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A12, A14, A16; A12′, A14′, A16′; A12″, A14″) of the first interconnect (B1; B1′; B1″) which lie in the first interconnect plane (M0) run at least in sections beside the interconnect sections (A22, A24; A22′; A24′; A21″, A23″) of the second interconnect (B2; B2′; B2″) which lie in the second interconnection plane (M1), and that the interconnect sections (A11, A13, A15; A11′, A13′, A15′; A11″, A13″) of the first interconnect (B1; B1′; B1″) which lie in the second interconnect plane (M1) run at least in sections beside the interconnect sections (A21, A23, A25; A21′, A23′, A25′; A22″) of the second interconnect (B2; B2′; B2″) which lie in the first interconnect plane (M0). The invention also provides a corresponding fabrication method.
摘要翻译： 本发明涉及具有第一互连（B1; B1'; B1“）的集成电路（1）的互连结构，其由多个互连部分（A11-A16; A11'-A16'）组成; A11“-A14”），位于第一和第二互连平面（M0，M1）中; 和与第一互连（B1; B1'; B1“）相邻的第二互连（B2; B2'; B2”），它们由多个互连部分（A21-A25; A21'- A25“; A21”-A23“），位于第一和第二互连平面（M0，M1）中; 第一和第二互连（B1; B1'; B1“; B2; B2'; B2”）在纵向方向上彼此偏移，使得互连部分（A12，A14，A16; 位于第一互连平面（M0）中的第一互连（B1; B1'; B1“）的A12'，A14'，A16'; A12”，A14“）至少在互连部分旁边 位于第二互连平面（M1）中的第二互连（B2; B2'; B2“）的位置（A22，A24; A22'; A24'; A21”，A23“）， A11，A13，A
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公开(公告)号：US06738304B2
公开(公告)日：2004-05-18
申请号：US10283992
申请日：2002-10-30
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： According to one embodiment, a dynamic memory is provided. The dynamic memory can include a memory matrix having a plurality of memory cells arranged in rows and columns. The memory cells in a row can be connected by in each case one of a plurality of word lines. The memory cells in a column can be connected by in each case one of a plurality of bit lines. The dynamic memory can also include a sense amplifier for reading data from the memory cells via the plurality of bit lines. Further, the dynamic memory can include a row address decoder and a column address decoder for generating memory-internal address in a manner dependent on a memory-external address signal. The dynamic memory can also include a sequence control device for cyclically generating refresh addresses for carrying for carrying out a refresh operation of the memory cells.
摘要翻译： 根据一个实施例，提供动态存储器。 动态存储器可以包括具有以行和列排列的多个存储器单元的存储器矩阵。 在每种情况下，可以连接多行字线中的一行中的存储单元。 列中的存储单元可以在每种情况下连接多个位线中的一个。 动态存储器还可以包括用于经由多个位线从存储器单元读取数据的读出放大器。 此外，动态存储器可以包括行地址解码器和用于以取决于存储器 - 外部地址信号的方式产生存储器内部地址的列地址解码器。 动态存储器还可以包括用于循环产生刷新地址以执行对存储器单元进行刷新操作的序列控制装置。
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公开(公告)号：US20120138251A1
公开(公告)日：2012-06-07
申请号：US13314793
申请日：2011-12-08
申请人： Wolfgang Ruf , Markus Häussler , Stefan Schlegel , Jens Haessner
发明人： Wolfgang Ruf , Markus Häussler , Stefan Schlegel , Jens Haessner
IPC分类号： D21F1/06
摘要： Headbox for a machine to produce a fiber web, in particular a paper, cardboard or tissue web from at least one fibrous suspension, having a headbox nozzle comprising an upper nozzle wall and a lower nozzle wall, as well as two side walls tapering to form an outlet, and having an inner chamber through which the fibrous suspension flows in flow direction during operation of headbox, whereby on upper nozzle wall of headbox nozzle a baffle is arranged on the outlet side which is movable by way of several elements and which extends across machine width, and which has a baffle protrusion and a baffle immersion depth and which has at least two surfaces—an upstream ramp surface and a subsequent main surface contacted by a fibrous suspension during operation of headbox. The inventive headbox is characterized in that between ramp surface of baffle and main surface of baffle at least one refraction surface which is in contact during operation of headbox with a fibrous suspension is provided on baffle.
摘要翻译： 用于机器的流浆箱，用于从至少一个纤维悬浮液产生纤维网，特别是纸，纸板或纸巾纸，其具有包括上喷嘴壁和下喷嘴壁的流浆箱喷嘴，以及渐缩形成的两个侧壁 出口，并且具有内室，纤维悬浮液在流浆箱操作期间沿流动方向流动，由此在流浆箱喷嘴的上喷嘴壁上，挡板布置在出口侧，出口侧可通过若干元件移动并延伸穿过 机器宽度，并且其具有挡板突起和挡板浸入深度，并且具有至少两个表面 - 在流浆箱操作期间由纤维悬浮液接触的上游斜面和随后的主表面。 本发明的流浆箱的特征在于，在挡板的斜面和挡板的主表面之间，在挡板上提供了在具有纤维悬浮液的流浆箱操作期间接触的至少一个折射表面。
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公开(公告)号：US20110265968A1
公开(公告)日：2011-11-03
申请号：US13102688
申请日：2011-05-06
申请人： Wolfgang Ruf , Konstantin Fenkl , Markus Häußler
发明人： Wolfgang Ruf , Konstantin Fenkl , Markus Häußler
IPC分类号： D21F1/02
摘要： The invention relates to a headbox which comprises a feed device feeding the at least one fiber suspension, a perforated distribution pipe plate arranged immediately downstream thereof and having a plurality of channels arranged in lines and columns, an intermediate channel arranged downstream thereof, extending over the width of the headbox and having a plurality of means for dosing a fluid in partial fluid streams to the at least one fiber suspension in a preferably adjustable/controlled manner, the means being spaced apart from each other in the width direction of the headbox and the individual means comprising a plurality of dosing channels having respective dosing channel openings and an opening center line, arriving at different levels and being connected to a common supply channel. The headbox further comprises a downstream turbulence generator having a plurality of flow channels arranged in lines and columns and a headbox nozzle which is directly contiguous to the turbulence generator and which has a nozzle gap. The headbox according to the invention has a system pressure loss which is substantially composed of a first pressure loss between the feed device and the intermediate channel and a second pressure loss in the turbulence generator, the second pressure loss and the first pressure loss being in a ratio ranging from 8:1 to 1:1, preferably from 4:1 to 1:1, particularly from 2:1 to 1:1.
摘要翻译： 本发明涉及一种流浆箱，其包括供给至少一个纤维悬浮液的进料装置，一个布置在其下游的多孔分配管板，并且具有排列成直线和立柱的多个通道，布置在其下游的中间通道， 流浆箱的宽度并且具有多个用于将部分流体流中的流体以优选可调节/受控的方式计量至少一个纤维悬浮液的装置，所述装置在流浆箱的宽度方向上彼此间隔开， 各个装置包括具有相应配量通道开口和开口中心线的多个计量通道，达到不同的水平并连接到共同的供应通道。 流浆箱还包括下游湍流发生器，其具有以行和列排列的多个流动通道和与湍流发生器直接邻接且具有喷嘴间隙的流浆箱喷嘴。 根据本发明的流浆箱具有系统压力损失，其基本上由进料装置和中间通道之间的第一压力损失和湍流发生器中的第二压力损失构成，第二压力损失和第一压力损失在 比率为8:1至1:1，优选4:1至1:1，特别是2:1至1:1。
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公开(公告)号：US20090085596A1
公开(公告)日：2009-04-02
申请号：US11863900
申请日：2007-09-28
申请人： Wolfgang Ruf , Michael Schittenhelm
发明人： Wolfgang Ruf , Michael Schittenhelm
IPC分类号： G01R31/02
CPC分类号： G11C29/56 , G01R31/31926 , G11C2029/5602
摘要： A system for testing semiconductor devices is disclosed. In one embodiment, the test system being configured to be electrically connected via parallel wiring paths to a plurality of contact pins of a number of devices under test. The test system having at least one signal distribution matrix arranged in the wiring path to provide signals for testing and/or power supply to the devices.
摘要翻译： 公开了一种半导体器件测试系统。 在一个实施例中，测试系统被配置为通过并行布线路径电连接到多个待测器件的接触引脚。 所述测试系统具有布置在所述布线路径中的至少一个信号分配矩阵，以提供用于测试和/或向所述设备供电的信号。
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公开(公告)号：US20080288835A1
公开(公告)日：2008-11-20
申请号：US12050706
申请日：2008-03-18
申请人： Wolfgang Ruf , Martin Schnell
发明人： Wolfgang Ruf , Martin Schnell
CPC分类号： G11C29/06 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/20 , G11C29/40 , G11C2029/3602
摘要： The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.
摘要翻译： 本文公开的测试方法，集成电路和测试系统实施例涉及测试至少一个集成电路，其使用内部操作时钟并具有第一数量的地址引脚，第二数量的命令引脚和至少接收到的地址产生电路 一个编码的地址信息项，其使用小于第一个数字的第三个地址引脚数，并将另一个地址引脚提供为第四个空闲地址引脚，其中使用命令引脚传送至少一个第一命令， 使用具有比内部操作时钟更低的速率的测试时钟，使用第四数量的地址引脚的至少一部分从测试装置传输到集成电路的至少一个第二命令。
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