-
1.发明授权Method for storing data in a memory device with the possibility of access to redundant memory cells 有权将数据存储在具有访问冗余存储单元的可能性的存储器件中的方法公开(公告)号：US06819606B2
公开(公告)日：2004-11-16
申请号：US10339031
申请日：2003-01-09
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： A method is provided for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns. The method can include a step for providing redundant memory cells in the memory device. The method can also include a step for localizing defective cells. Further, the method can include a step of accessing the redundant memory cells by means of a predeterminable access mode. The method can also include a step of bypassing defective memory cells of the memory device in a manner dependent on the predeterminable access mode during operation of the memory device for accessing redundant memory cells and for replacement by redundant memory cells. Further, the method can include a step for providing redundant memory cells for storing additional information describing a defect correction.
摘要翻译： 提供了一种用于将数据存储在具有布置在存储单元行和存储单元列中的存储单元的存储器件中的方法。 该方法可以包括在存储器件中提供冗余存储器单元的步骤。 该方法还可以包括用于定位缺陷单元的步骤。 此外，该方法可以包括通过可预定访问模式访问冗余存储器单元的步骤。 该方法还可以包括在存储器设备的操作期间以取决于可预定访问模式的方式绕过存储器件的有缺陷的存储单元的步骤，用于访问冗余存储器单元并由冗余存储器单元替换。 此外，该方法可以包括用于提供用于存储描述缺陷校正的附加信息的冗余存储器单元的步骤。
-
2.发明授权公开(公告)号：US06806121B2
公开(公告)日：2004-10-19
申请号：US10285090
申请日：2002-10-31
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an interconnect structure for an integrated circuit (1) having a first interconnect (B1; B1′; B1″), which is composed of a plurality of interconnect sections (A11-A16; A11′-A16′; A11″-A14″) lying in a first and a second interconnect plane (M0, M1); and a second interconnect (B2; B2′; B2″), which runs adjacent to the first interconnect (B1; B1′; B1″) and which is composed of a plurality of interconnect sections (A21-A25; A21′-A25′; A21″-A23″) lying in the first and second interconnect planes (M0, M1); the first and second interconnects (B1; B1′; B1″; B2; B2′; B2″) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A12, A14, A16; A12′, A14′, A16′; A12″, A14″) of the first interconnect (B1; B1′; B1″) which lie in the first interconnect plane (M0) run at least in sections beside the interconnect sections (A22, A24; A22′; A24′; A21″, A23″) of the second interconnect (B2; B2′; B2″) which lie in the second interconnection plane (M1), and that the interconnect sections (A11, A13, A15; A11′, A13′, A15′; A11″, A13″) of the first interconnect (B1; B1′; B1″) which lie in the second interconnect plane (M1) run at least in sections beside the interconnect sections (A21, A23, A25; A21′, A23′, A25′; A22″) of the second interconnect (B2; B2′; B2″) which lie in the first interconnect plane (M0). The invention also provides a corresponding fabrication method.
摘要翻译： 本发明涉及具有第一互连（B1; B1'; B1“）的集成电路（1）的互连结构，其由多个互连部分（A11-A16; A11'-A16'）组成; A11“-A14”），位于第一和第二互连平面（M0，M1）中; 和与第一互连（B1; B1'; B1“）相邻的第二互连（B2; B2'; B2”），它们由多个互连部分（A21-A25; A21'- A25“; A21”-A23“），位于第一和第二互连平面（M0，M1）中; 第一和第二互连（B1; B1'; B1“; B2; B2'; B2”）在纵向方向上彼此偏移，使得互连部分（A12，A14，A16; 位于第一互连平面（M0）中的第一互连（B1; B1'; B1“）的A12'，A14'，A16'; A12”，A14“）至少在互连部分旁边 位于第二互连平面（M1）中的第二互连（B2; B2'; B2“）的位置（A22，A24; A22'; A24'; A21”，A23“）， A11，A13，A
-
公开(公告)号：US06738304B2
公开(公告)日：2004-05-18
申请号：US10283992
申请日：2002-10-30
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： According to one embodiment, a dynamic memory is provided. The dynamic memory can include a memory matrix having a plurality of memory cells arranged in rows and columns. The memory cells in a row can be connected by in each case one of a plurality of word lines. The memory cells in a column can be connected by in each case one of a plurality of bit lines. The dynamic memory can also include a sense amplifier for reading data from the memory cells via the plurality of bit lines. Further, the dynamic memory can include a row address decoder and a column address decoder for generating memory-internal address in a manner dependent on a memory-external address signal. The dynamic memory can also include a sequence control device for cyclically generating refresh addresses for carrying for carrying out a refresh operation of the memory cells.
摘要翻译： 根据一个实施例，提供动态存储器。 动态存储器可以包括具有以行和列排列的多个存储器单元的存储器矩阵。 在每种情况下，可以连接多行字线中的一行中的存储单元。 列中的存储单元可以在每种情况下连接多个位线中的一个。 动态存储器还可以包括用于经由多个位线从存储器单元读取数据的读出放大器。 此外，动态存储器可以包括行地址解码器和用于以取决于存储器 - 外部地址信号的方式产生存储器内部地址的列地址解码器。 动态存储器还可以包括用于循环产生刷新地址以执行对存储器单元进行刷新操作的序列控制装置。
-
公开(公告)号：US07065687B2
公开(公告)日：2006-06-20
申请号：US10253465
申请日：2002-09-24
摘要： A method for replacing defective memory cells of a random access memory device of a data processing apparatus, in which, during the operation of the data processing apparatus, a defective memory cell is replaced by a replacement memory cell in the random access memory device by using a control instruction.
-
5.发明授权Method for integrating imperfect semiconductor memory devices in data processing apparatus 有权在数据处理装置中集成不完美的半导体存储器件的方法公开(公告)号：US06762965B2
公开(公告)日：2004-07-13
申请号：US10254694
申请日：2002-09-25
IPC分类号： G11C700
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A method for integrating imperfect semiconductor memory devices having functional and defective memory cells into a data processing apparatus. The defective memory cells are assigned defect addresses or defect address ranges. Before a memory access of the data processing apparatus is carried out, the address of the memory access is compared with the defect addresses or defect address ranges and is recoded in the event of correspondence.
摘要翻译： 一种用于将具有功能和缺陷存储器单元的不完美半导体存储器件集成到数据处理装置中的方法。 缺陷存储单元被分配缺陷地址或缺陷地址范围。 在执行数据处理装置的存储器访问之前，将存储器访问的地址与缺陷地址或缺陷地址范围进行比较，并且在对应的情况下被重新编码。
-
6.发明授权公开(公告)号：US07305525B2
公开(公告)日：2007-12-04
申请号：US11132419
申请日：2005-05-19
CPC分类号： H04N21/2182 , G11C7/1018 , G11C7/103 , H04N21/23116 , H04N21/2312 , H04N21/2323
摘要： A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a respective dedicated output for interchanging data. The inputs of a matrix switch are connected to a respective output of a different memory unit. The matrix switch is operated such that a plurality of the memory units are connected to its output in a sequential order. A first sequence of memory units and a second sequence of memory units are connected to its output independently. This results in a memory system, which can handle a number of requests to the same memory at staggered times. The interaction of the individual memory units with the matrix switch allows a high data throughput and a short access time.
摘要翻译： 用于诸如视频/音频应用的网络广播应用的存储器系统具有至少一个存储器，其被分成多个可寻址存储器单元，其具有用于交换数据的相应的专用输出。 矩阵开关的输入端连接到不同存储器单元的相应输出端。 矩阵开关的操作使得多个存储器单元以其顺序连接到其输出。 存储单元的第一序列和第二存储单元序列独立地连接到其输出。 这导致存储器系统，其可以以交错的时间处理对相同存储器的多个请求。 单个存储器单元与矩阵开关的交互允许高数据吞吐量和短的访问时间。
-
7.发明申请公开(公告)号：US20050248994A1
公开(公告)日：2005-11-10
申请号：US11132419
申请日：2005-05-19
CPC分类号： H04N21/2182 , G11C7/1018 , G11C7/103 , H04N21/23116 , H04N21/2312 , H04N21/2323
摘要： A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a respective dedicated output for interchanging data. The inputs of a matrix switch are connected to a respective output of a different memory unit. The matrix switch is operated such that a plurality of the memory units are connected to its output in a sequential order. A first sequence of memory units and a second sequence of memory units are connected to its output independently. This results in a memory system, which can handle a number of requests to the same memory at staggered times. The interaction of the individual memory units with the matrix switch allows a high data throughput and a short access time.
摘要翻译： 用于诸如视频/音频应用的网络广播应用的存储器系统具有至少一个存储器，其被分成多个可寻址存储器单元，其具有用于交换数据的相应的专用输出。 矩阵开关的输入端连接到不同存储器单元的相应输出端。 矩阵开关的操作使得多个存储器单元以其顺序连接到其输出。 存储单元的第一序列和第二存储单元序列独立地连接到其输出。 这导致存储器系统，其可以以交错的时间处理对相同存储器的多个请求。 单个存储器单元与矩阵开关的交互允许高数据吞吐量和短的访问时间。
-
公开(公告)号：US06876217B2
公开(公告)日：2005-04-05
申请号：US10272344
申请日：2002-10-15
CPC分类号： G11C29/40 , G11C2029/2602
摘要： To be able to test a plurality of identical semiconductor circuit devices in a particularly rapid yet reliable manner, a test method includes carrying out the tests in parallel and substantially simultaneously on the plurality of semiconductor circuit devices and driver lines—used in the process—of a test device to the semiconductor circuit devices simultaneously and jointly for all the semiconductor circuit devices. In such a case, test results are read from a plurality of input/output channels in compressed form. Furthermore, as an alternative or in addition thereto, the semiconductor circuit devices to be tested are disposed and connected up in at least one stack.
摘要翻译： 为了能够以特别快速且可靠的方式测试多个相同的半导体电路器件，测试方法包括并行并且基本上同时地在用于该过程的多个半导体电路器件和驱动器线路上执行测试 用于半导体电路装置的测试装置，同时并共同地用于所有半导体电路装置。 在这种情况下，从压缩形式的多个输入/输出通道读取测试结果。 此外，作为替代或补充，待测试的半导体电路器件被布置并连接到至少一个堆叠中。
-
公开(公告)号：US06829554B2
公开(公告)日：2004-12-07
申请号：US10109545
申请日：2002-03-28
IPC分类号： G01K500
CPC分类号： G11C29/50 , G11C29/006
摘要： A method for classifying semiconductor components by their performance characteristics includes reading an identifier associated with a component and storing, in conjunction with the identifier, first and second performances values for that component. These performance values represent the component's achieved operating speed at each of two different temperatures. The component is then allocated to a speed category on the basis of the first and second performance values.
摘要翻译： 通过其性能特征对半导体组件进行分类的方法包括读取与组件相关联的标识符，并与该标识符一起存储该组件的第一和第二性能值。 这些性能值代表组件在两个不同温度下的实现运行速度。 然后基于第一和第二性能值将组件分配给速度类别。
-
10.发明授权Testing a data store using an external test unit for generating test sequence and receiving compressed test results 失效使用外部测试单元测试数据存储，以生成测试序列并接收压缩测试结果公开(公告)号：US07428662B2
公开(公告)日：2008-09-23
申请号：US10478403
申请日：2002-05-15
IPC分类号： G06F11/00 , G06F11/277
摘要： Disclosed is a test method for testing a data store having an integrated test data compression circuit where the data store has a memory cell array with a multiplicity of addressable memory cells, read/write amplifiers for reading and writing data to the memory cell via an internal data bus in the data store and a test data compression circuit which compresses test data sequences, which are each read serially from the memory cell array, with stored reference test data sequences in order to produce a respective indicator data item which indicates whether at least one data error has occurred in the test data sequence which has been read.
摘要翻译： 公开了一种用于测试具有集成测试数据压缩电路的数据存储器的测试方法，其中数据存储器具有具有多个可寻址存储器单元的存储单元阵列，用于经由内部存储器单元向存储器单元读取和写入数据的读/写放大器 数据存储器中的数据总线和压缩从存储单元阵列中串行读取的测试数据序列的测试数据压缩电路与存储的参考测试数据序列一起，以产生相应的指示符数据项，该指示符数据项指示是否至少一个 已经读取的测试数据序列中发生了数据错误。
-
-
-
-
-
-
-
-
-
搜索结果
95 条记录 (耗时 0.02 秒)
