-
公开(公告)号：US07065687B2
公开(公告)日：2006-06-20
申请号：US10253465
申请日：2002-09-24
摘要： A method for replacing defective memory cells of a random access memory device of a data processing apparatus, in which, during the operation of the data processing apparatus, a defective memory cell is replaced by a replacement memory cell in the random access memory device by using a control instruction.
-
公开(公告)号：US06522588B2
公开(公告)日：2003-02-18
申请号：US09932893
申请日：2001-08-20
申请人： Alexander Benedix
发明人： Alexander Benedix
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1039 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A description is given of a method and a device for outputting data via a buffer memory. In which the data, which are intended to be output first from the buffer memory are selected. The selected data are written either to a predetermined area of the buffer memory and/or to the buffer memory temporally before the rest of the data and output.
-
3.发明授权Testing a data store using an external test unit for generating test sequence and receiving compressed test results 失效使用外部测试单元测试数据存储，以生成测试序列并接收压缩测试结果公开(公告)号：US07428662B2
公开(公告)日：2008-09-23
申请号：US10478403
申请日：2002-05-15
IPC分类号： G06F11/00 , G06F11/277
摘要： Disclosed is a test method for testing a data store having an integrated test data compression circuit where the data store has a memory cell array with a multiplicity of addressable memory cells, read/write amplifiers for reading and writing data to the memory cell via an internal data bus in the data store and a test data compression circuit which compresses test data sequences, which are each read serially from the memory cell array, with stored reference test data sequences in order to produce a respective indicator data item which indicates whether at least one data error has occurred in the test data sequence which has been read.
摘要翻译： 公开了一种用于测试具有集成测试数据压缩电路的数据存储器的测试方法，其中数据存储器具有具有多个可寻址存储器单元的存储单元阵列，用于经由内部存储器单元向存储器单元读取和写入数据的读/写放大器 数据存储器中的数据总线和压缩从存储单元阵列中串行读取的测试数据序列的测试数据压缩电路与存储的参考测试数据序列一起，以产生相应的指示符数据项，该指示符数据项指示是否至少一个 已经读取的测试数据序列中发生了数据错误。
-
公开(公告)号：US07127553B2
公开(公告)日：2006-10-24
申请号：US10717337
申请日：2003-11-19
申请人： Alexander Benedix , Georg Braun , Bernd Klehn
发明人： Alexander Benedix , Georg Braun , Bernd Klehn
IPC分类号： H01L27/108
CPC分类号： G06F11/3409
摘要： A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.
摘要翻译： 用于执行数据处理过程的配置具有由操作系统使用用于执行系统进程的访问策略来访问的操作系统和各种系统资源。 当有不同的应用程序时，使用与系统资源不同的访问策略。 还提供了一种用于确定对系统资源的最佳访问策略的方法。
-
5.发明授权Method for testing a device and a test configuration including a device with a test memory 有权用于测试设备的方法和包括具有测试存储器的设备的测试配置公开(公告)号：US06895538B2
公开(公告)日：2005-05-17
申请号：US09907694
申请日：2001-07-18
IPC分类号： G11C29/44 , H01L23/544 , G11C29/00
CPC分类号： H01L23/544 , G11C29/44 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： A test configuration that includes a device and a method for testing the device in which test results determined during the testing of the device are stored in a memory in the device. In this way, the test results are connected with the device and available at any time for later evaluations.
摘要翻译： 包括用于测试设备的测试配置和测试设备的方法，其中在设备测试期间确定测试结果被存储在设备中的存储器中。 以这种方式，测试结果与设备连接，随时可用于以后的评估。
-
6.发明授权Method for storing data in a memory device with the possibility of access to redundant memory cells 有权将数据存储在具有访问冗余存储单元的可能性的存储器件中的方法公开(公告)号：US06819606B2
公开(公告)日：2004-11-16
申请号：US10339031
申请日：2003-01-09
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： A method is provided for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns. The method can include a step for providing redundant memory cells in the memory device. The method can also include a step for localizing defective cells. Further, the method can include a step of accessing the redundant memory cells by means of a predeterminable access mode. The method can also include a step of bypassing defective memory cells of the memory device in a manner dependent on the predeterminable access mode during operation of the memory device for accessing redundant memory cells and for replacement by redundant memory cells. Further, the method can include a step for providing redundant memory cells for storing additional information describing a defect correction.
摘要翻译： 提供了一种用于将数据存储在具有布置在存储单元行和存储单元列中的存储单元的存储器件中的方法。 该方法可以包括在存储器件中提供冗余存储器单元的步骤。 该方法还可以包括用于定位缺陷单元的步骤。 此外，该方法可以包括通过可预定访问模式访问冗余存储器单元的步骤。 该方法还可以包括在存储器设备的操作期间以取决于可预定访问模式的方式绕过存储器件的有缺陷的存储单元的步骤，用于访问冗余存储器单元并由冗余存储器单元替换。 此外，该方法可以包括用于提供用于存储描述缺陷校正的附加信息的冗余存储器单元的步骤。
-
7.发明授权Integrated circuit with temperature sensor and method for heating the circuit 失效具有温度传感器的集成电路和加热电路的方法公开(公告)号：US06798706B2
公开(公告)日：2004-09-28
申请号：US10352824
申请日：2003-01-28
IPC分类号： G11C704
CPC分类号： G01K7/01
摘要： A temperature sensor is integrated together with an integrated circuit on a chip, the sensor delivering a temperature-dependent measuring signal or at least emitting a signal when the chip temperature falls below a specific prescribed value. For such an eventuality, the chip includes a special circuit device thereon, by which a current flow is generated through a provided structure of electrical conductors that keeps the temperature of the integrated circuit above a prescribed minimum temperature.
摘要翻译： 温度传感器与芯片上的集成电路集成在一起，传感器传递温度相关的测量信号，或者当芯片温度低于特定规定值时至少发出信号。 对于这样的可能性，芯片包括其上的专用电路装置，通过该电路，电流通过提供的集成电路的温度高于预定的最低温度的电导体的结构产生。
-
8.发明授权公开(公告)号：US07305525B2
公开(公告)日：2007-12-04
申请号：US11132419
申请日：2005-05-19
CPC分类号： H04N21/2182 , G11C7/1018 , G11C7/103 , H04N21/23116 , H04N21/2312 , H04N21/2323
摘要： A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a respective dedicated output for interchanging data. The inputs of a matrix switch are connected to a respective output of a different memory unit. The matrix switch is operated such that a plurality of the memory units are connected to its output in a sequential order. A first sequence of memory units and a second sequence of memory units are connected to its output independently. This results in a memory system, which can handle a number of requests to the same memory at staggered times. The interaction of the individual memory units with the matrix switch allows a high data throughput and a short access time.
摘要翻译： 用于诸如视频/音频应用的网络广播应用的存储器系统具有至少一个存储器，其被分成多个可寻址存储器单元，其具有用于交换数据的相应的专用输出。 矩阵开关的输入端连接到不同存储器单元的相应输出端。 矩阵开关的操作使得多个存储器单元以其顺序连接到其输出。 存储单元的第一序列和第二存储单元序列独立地连接到其输出。 这导致存储器系统，其可以以交错的时间处理对相同存储器的多个请求。 单个存储器单元与矩阵开关的交互允许高数据吞吐量和短的访问时间。
-
9.发明申请公开(公告)号：US20050248994A1
公开(公告)日：2005-11-10
申请号：US11132419
申请日：2005-05-19
CPC分类号： H04N21/2182 , G11C7/1018 , G11C7/103 , H04N21/23116 , H04N21/2312 , H04N21/2323
摘要： A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a respective dedicated output for interchanging data. The inputs of a matrix switch are connected to a respective output of a different memory unit. The matrix switch is operated such that a plurality of the memory units are connected to its output in a sequential order. A first sequence of memory units and a second sequence of memory units are connected to its output independently. This results in a memory system, which can handle a number of requests to the same memory at staggered times. The interaction of the individual memory units with the matrix switch allows a high data throughput and a short access time.
摘要翻译： 用于诸如视频/音频应用的网络广播应用的存储器系统具有至少一个存储器，其被分成多个可寻址存储器单元，其具有用于交换数据的相应的专用输出。 矩阵开关的输入端连接到不同存储器单元的相应输出端。 矩阵开关的操作使得多个存储器单元以其顺序连接到其输出。 存储单元的第一序列和第二存储单元序列独立地连接到其输出。 这导致存储器系统，其可以以交错的时间处理对相同存储器的多个请求。 单个存储器单元与矩阵开关的交互允许高数据吞吐量和短的访问时间。
-
10.发明授权公开(公告)号：US06798051B2
公开(公告)日：2004-09-28
申请号：US10197793
申请日：2002-07-18
IPC分类号： H01L2302
CPC分类号： H05K1/141 , H01L25/0652 , H01L2224/48091 , H05K1/145 , H05K3/3447 , H05K2201/10287 , H05K2201/10325 , H05K2201/10522 , H05K2201/1053 , H05K2201/10689 , H01L2924/00014
摘要： An interface unit and a printed circuit board configuration includes at least two interface units for linking conventional commercially available packages of integrated circuits on a printed circuit board in a more flexible and compact way, which allows compact high-performance electronic circuits to be produced on a small surface area and with low development expenditure.
摘要翻译： 接口单元和印刷电路板配置包括至少两个接口单元，用于以更灵活和紧凑的方式将印刷电路板上的常规商业可用的集成电路封装连接起来，这使得可以在紧凑型高性能电子电路 表面积小，开发费用低。
-
-
-
-
-
-
-
-
-
搜索结果
21 条记录 (耗时 0.012 秒)
