公开(公告)号：US20170068051A1

公开(公告)日：2017-03-09

申请号：US15243746

申请日：2016-08-22

Applicant: Renesas Electronics Corporation ,  Photonics Electronics Technology Research Association

Inventor： Shinichi WATANUKI ,  Akira MITSUIKl ,  Atsuro INADA ,  Tohru MOGAMI ,  Tsuyoshi HORIKAWA ,  Keizo KINOSHITA

IPC: G02B6/136 ,  G02B6/122

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/122 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02F1/025 ,  G02F2201/063 ,  G02F2201/066 ,  G02F2202/105

Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.

Abstract translation: 当形成光波导时，抗蚀剂掩模的开口面积等于从抗蚀剂掩模露出的虚拟图案的半导体层的面积，并且从抗蚀剂掩模露出的伪图案的半导体层具有 在其中形成虚拟图案的区域中具有均匀的厚度。 结果，对于伪图案的半导体层的蚀刻，有效图案密度不变，因此，可以形成具有所需尺寸和期望形状的肋状光波导。

公开(公告)号：US20160282554A1

公开(公告)日：2016-09-29

申请号：US15062153

申请日：2016-03-06

Applicant: Renesas Electronics Corporation

Inventor： Shinichi WATANUKI ,  Atsuro INADA

IPC: G02B6/122 ,  G02B6/136

CPC classification number: H01L31/18 ,  G02B6/122 ,  G02B6/1223 ,  G02B6/13 ,  G02B6/136 ,  G02F1/025 ,  H01L31/02325

Abstract: A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air.

Abstract translation: 半导体衬底，形成在半导体衬底上的由氧化硅制成的绝缘层和形成在绝缘层上的由硅制成的半导体层，并且半导体层构成光信号传输线段中的光波导和光调制器 在光调制部分中。 此外，绝缘层除了其一部分之外被除去以具有空腔的中空结构，并且构成光波导和光调制器的每个半导体层的两个侧表面和下表面暴露并被空气覆盖。

公开(公告)号：US20170263802A1

公开(公告)日：2017-09-14

申请号：US15606281

申请日：2017-05-26

Applicant: Renesas Electronics Corporation

Inventor： Shinichi WATANUKI ,  Atsuro INADA

IPC: H01L31/18 ,  H01L31/0232

CPC classification number: H01L31/18 ,  G02B6/122 ,  G02B6/1223 ,  G02B6/13 ,  G02B6/136 ,  G02F1/025 ,  H01L31/02325

Abstract: A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air.

公开(公告)号：US20180136391A1

公开(公告)日：2018-05-17

申请号：US15871569

申请日：2018-01-15

Applicant: Renesas Electronics Corporation

Inventor： Atsuro INADA

IPC: G02B6/122 ,  G02B6/136 ,  G02B6/12

CPC classification number: G02B6/136 ,  G02B6/122 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/12176

Abstract: First, half etching is performed to a semiconductor layer formed on an insulating layer to form trenches at positions of slab-portion regions in which slab portions are to be formed. After filling the trenches with an insulating film, a resist mask which covers the semiconductor layer at a projecting-portion region in which a projecting portion is to be formed and whose pattern ends are located on upper surfaces of the insulating films is formed on upper surfaces of the semiconductor layer and the insulating film, and full etching is performed to the semiconductor layer with using the resist mask and the insulating film as an etching mask, thereby forming an optical waveguide constituted of the projecting portion and the slab portions. Thereafter, a first interlayer insulating film is formed to cover the optical waveguide.

公开(公告)号：US20170038530A1

公开(公告)日：2017-02-09

申请号：US15212170

申请日：2016-07-15

Applicant: Renesas Electronics Corporation

Inventor： Atsuro INADA

IPC: G02B6/122 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/136 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12097

Abstract: First, half etching is performed to a semiconductor layer formed on an insulating layer to form trenches at positions of slab-portion regions in which slab portions are to be formed. After filling the trenches with an insulating film, a resist mask which covers the semiconductor layer at a projecting-portion region in which a projecting portion is to be formed and whose pattern ends are located on upper surfaces of the insulating films is formed on upper surfaces of the semiconductor layer and the insulating film, and full etching is performed to the semiconductor layer with using the resist mask and the insulating film as an etching mask, thereby forming an optical waveguide constituted of the projecting portion and the slab portions. Thereafter, a first interlayer insulating film is formed to cover the optical waveguide.

Abstract translation: 首先，对形成在绝缘层上的半导体层进行半蚀刻，以在要形成板坯部分的板坯区域的位置上形成沟槽。 在用绝缘膜填充沟槽之后，在形成有突出部分的突出部分区域并且其图案末端位于绝缘膜的上表面上的抗蚀剂掩模形成在上表面 的半导体层和绝缘膜，并且通过使用抗蚀剂掩模和绝缘膜作为蚀刻掩模对半导体层进行全蚀刻，从而形成由突出部分和板坯部分构成的光波导。 此后，形成第一层间绝缘膜以覆盖光波导。